radv/ac: add clip support for tess eval shader.

[mesa.git] / src / amd / common / ac_nir_to_llvm.c

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1666de4081b1f0a6ff6ddc1c82c196088d1a1171..32f5f6564dcf61cf88babfdc115a986da8258788 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4320,6 +4320,7 @@ handle_shader_output_decl(struct nir_to_llvm_context *ctx,
 
        mask_attribs = ((1ull << attrib_count) - 1) << idx;
        if (ctx->stage == MESA_SHADER_VERTEX ||
+           ctx->stage == MESA_SHADER_TESS_EVAL ||
            ctx->stage == MESA_SHADER_GEOMETRY) {
                if (idx == VARYING_SLOT_CLIP_DIST0) {
                        int length = ctx->num_output_clips + ctx->num_output_culls;
@@ -4327,6 +4328,10 @@ handle_shader_output_decl(struct nir_to_llvm_context *ctx,
                                ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
                                ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
                        }
+                       if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+                               ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
+                               ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
+                       }
 
                        if (length > 4)
                                attrib_count = 2;