#include "../vulkan/radv_descriptor_set.h"
#include "util/bitscan.h"
#include <llvm-c/Transforms/Scalar.h>
+#include "ac_shader_info.h"
+#include "ac_exp_param.h"
enum radeon_llvm_calling_convention {
RADEON_LLVM_AMDGPU_VS = 87,
struct ac_llvm_context ac;
const struct ac_nir_compiler_options *options;
struct ac_shader_variant_info *shader_info;
-
+ unsigned max_workgroup_size;
LLVMContextRef context;
LLVMModuleRef module;
LLVMBuilderRef builder;
LLVMValueRef hs_ring_tess_factor;
LLVMValueRef prim_mask;
- LLVMValueRef sample_positions;
+ LLVMValueRef sample_pos_offset;
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
LLVMValueRef front_face;
LLVMBuilderRef builder, LLVMTypeRef *return_types,
unsigned num_return_elems, LLVMTypeRef *param_types,
unsigned param_count, unsigned array_params_mask,
- unsigned sgpr_params, bool unsafe_math)
+ unsigned sgpr_params, unsigned max_workgroup_size,
+ bool unsafe_math)
{
LLVMTypeRef main_function_type, ret_type;
LLVMBasicBlockRef main_function_body;
}
}
+ if (max_workgroup_size) {
+ ac_llvm_add_target_dep_function_attr(main_function,
+ "amdgpu-max-work-group-size",
+ max_workgroup_size);
+ }
if (unsafe_math) {
/* These were copied from some LLVM test. */
LLVMAddTargetDependentFunctionAttr(main_function,
set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
}
-#if 0
+
static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
uint32_t indirect_offset)
{
ud_info->indirect = true;
ud_info->indirect_offset = indirect_offset;
}
-#endif
-static void create_function(struct nir_to_llvm_context *ctx)
+static void declare_tess_lds(struct nir_to_llvm_context *ctx)
{
- LLVMTypeRef arg_types[23];
- unsigned arg_idx = 0;
- unsigned array_params_mask = 0;
- unsigned sgpr_count = 0, user_sgpr_count;
- unsigned i;
- unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
- unsigned user_sgpr_idx;
- bool need_push_constants;
- bool need_ring_offsets = false;
+ unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
+ ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
+ LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
+ "tess_lds");
+}
+
+struct user_sgpr_info {
+ bool need_ring_offsets;
+ uint8_t sgpr_count;
+ bool indirect_all_descriptor_sets;
+};
+
+static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
+ struct user_sgpr_info *user_sgpr_info)
+{
+ memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
/* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
if (ctx->stage == MESA_SHADER_GEOMETRY ||
ctx->stage == MESA_SHADER_TESS_CTRL ||
ctx->stage == MESA_SHADER_TESS_EVAL ||
ctx->is_gs_copy_shader)
- need_ring_offsets = true;
+ user_sgpr_info->need_ring_offsets = true;
- need_push_constants = true;
- if (!ctx->options->layout)
- need_push_constants = false;
- else if (!ctx->options->layout->push_constant_size &&
- !ctx->options->layout->dynamic_offset_count)
- need_push_constants = false;
+ if (ctx->stage == MESA_SHADER_FRAGMENT &&
+ ctx->shader_info->info.ps.needs_sample_positions)
+ user_sgpr_info->need_ring_offsets = true;
- if (need_ring_offsets && !ctx->options->supports_spill) {
- arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
+ /* 2 user sgprs will nearly always be allocated for scratch/rings */
+ if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
+ user_sgpr_info->sgpr_count += 2;
+ }
+
+ switch (ctx->stage) {
+ case MESA_SHADER_COMPUTE:
+ user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
+ break;
+ case MESA_SHADER_FRAGMENT:
+ user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
+ break;
+ case MESA_SHADER_VERTEX:
+ if (!ctx->is_gs_copy_shader) {
+ user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
+ if (ctx->shader_info->info.vs.needs_draw_id) {
+ user_sgpr_info->sgpr_count += 3;
+ } else {
+ user_sgpr_info->sgpr_count += 2;
+ }
+ }
+ if (ctx->options->key.vs.as_ls)
+ user_sgpr_info->sgpr_count++;
+ break;
+ case MESA_SHADER_TESS_CTRL:
+ user_sgpr_info->sgpr_count += 4;
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ user_sgpr_info->sgpr_count += 1;
+ break;
+ case MESA_SHADER_GEOMETRY:
+ user_sgpr_info->sgpr_count += 2;
+ break;
+ default:
+ break;
+ }
+
+ if (ctx->shader_info->info.needs_push_constants)
+ user_sgpr_info->sgpr_count += 2;
+
+ uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
+ if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
+ user_sgpr_info->sgpr_count += 2;
+ user_sgpr_info->indirect_all_descriptor_sets = true;
+ } else {
+ user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
+ }
+}
+
+static void create_function(struct nir_to_llvm_context *ctx)
+{
+ LLVMTypeRef arg_types[23];
+ unsigned arg_idx = 0;
+ unsigned array_params_mask = 0;
+ unsigned sgpr_count = 0, user_sgpr_count;
+ unsigned i;
+ unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
+ unsigned user_sgpr_idx;
+ struct user_sgpr_info user_sgpr_info;
+
+ allocate_user_sgprs(ctx, &user_sgpr_info);
+ if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
+ arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
}
/* 1 for each descriptor set */
- for (unsigned i = 0; i < num_sets; ++i) {
- if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
- array_params_mask |= (1 << arg_idx);
- arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
+ if (!user_sgpr_info.indirect_all_descriptor_sets) {
+ for (unsigned i = 0; i < num_sets; ++i) {
+ if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
+ array_params_mask |= (1 << arg_idx);
+ arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
+ }
}
+ } else {
+ array_params_mask |= (1 << arg_idx);
+ arg_types[arg_idx++] = const_array(const_array(ctx->i8, 1024 * 1024), 32);
}
- if (need_push_constants) {
+ if (ctx->shader_info->info.needs_push_constants) {
/* 1 for push constants and dynamic descriptors */
array_params_mask |= (1 << arg_idx);
arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
switch (ctx->stage) {
case MESA_SHADER_COMPUTE:
- arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
+ if (ctx->shader_info->info.cs.grid_components_used)
+ arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
user_sgpr_count = arg_idx;
arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
arg_types[arg_idx++] = ctx->i32;
break;
case MESA_SHADER_VERTEX:
if (!ctx->is_gs_copy_shader) {
- arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
+ if (ctx->shader_info->info.vs.has_vertex_buffers)
+ arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
arg_types[arg_idx++] = ctx->i32; // base vertex
arg_types[arg_idx++] = ctx->i32; // start instance
- arg_types[arg_idx++] = ctx->i32; // draw index
+ if (ctx->shader_info->info.vs.needs_draw_id)
+ arg_types[arg_idx++] = ctx->i32; // draw index
}
user_sgpr_count = arg_idx;
if (ctx->options->key.vs.as_es)
arg_types[arg_idx++] = ctx->i32; // GS instance id
break;
case MESA_SHADER_FRAGMENT:
- arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
+ if (ctx->shader_info->info.ps.needs_sample_positions)
+ arg_types[arg_idx++] = ctx->i32; /* sample position offset */
user_sgpr_count = arg_idx;
arg_types[arg_idx++] = ctx->i32; /* prim mask */
sgpr_count = arg_idx;
ctx->main_function = create_llvm_function(
ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
- arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
+ arg_idx, array_params_mask, sgpr_count, ctx->max_workgroup_size,
+ ctx->options->unsafe_math);
set_llvm_calling_convention(ctx->main_function, ctx->stage);
ctx->shader_info->num_input_sgprs = 0;
arg_idx = 0;
user_sgpr_idx = 0;
- if (ctx->options->supports_spill || need_ring_offsets) {
+ if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
user_sgpr_idx += 2;
if (ctx->options->supports_spill) {
LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
NULL, 0, AC_FUNC_ATTR_READNONE);
ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
- const_array(ctx->v16i8, 8), "");
+ const_array(ctx->v16i8, 16), "");
} else
ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
}
- for (unsigned i = 0; i < num_sets; ++i) {
- if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
- set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
- user_sgpr_idx += 2;
- ctx->descriptor_sets[i] =
- LLVMGetParam(ctx->main_function, arg_idx++);
- } else
- ctx->descriptor_sets[i] = NULL;
+ if (!user_sgpr_info.indirect_all_descriptor_sets) {
+ for (unsigned i = 0; i < num_sets; ++i) {
+ if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
+ set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
+ user_sgpr_idx += 2;
+ ctx->descriptor_sets[i] =
+ LLVMGetParam(ctx->main_function, arg_idx++);
+ } else
+ ctx->descriptor_sets[i] = NULL;
+ }
+ } else {
+ uint32_t desc_sgpr_idx = user_sgpr_idx;
+ LLVMValueRef desc_sets = LLVMGetParam(ctx->main_function, arg_idx++);
+ set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
+ user_sgpr_idx += 2;
+
+ for (unsigned i = 0; i < num_sets; ++i) {
+ if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
+ set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
+ ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
+
+ } else
+ ctx->descriptor_sets[i] = NULL;
+ }
+ ctx->shader_info->need_indirect_descriptor_sets = true;
}
- if (need_push_constants) {
+ if (ctx->shader_info->info.needs_push_constants) {
ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
user_sgpr_idx += 2;
switch (ctx->stage) {
case MESA_SHADER_COMPUTE:
- set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
- user_sgpr_idx += 3;
- ctx->num_work_groups =
- LLVMGetParam(ctx->main_function, arg_idx++);
+ if (ctx->shader_info->info.cs.grid_components_used) {
+ set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
+ user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
+ ctx->num_work_groups =
+ LLVMGetParam(ctx->main_function, arg_idx++);
+ }
ctx->workgroup_ids =
LLVMGetParam(ctx->main_function, arg_idx++);
ctx->tg_size =
break;
case MESA_SHADER_VERTEX:
if (!ctx->is_gs_copy_shader) {
- set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
- user_sgpr_idx += 2;
- ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
- set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
- user_sgpr_idx += 3;
+ if (ctx->shader_info->info.vs.has_vertex_buffers) {
+ set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
+ user_sgpr_idx += 2;
+ ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
+ }
+ unsigned vs_num = 2;
+ if (ctx->shader_info->info.vs.needs_draw_id)
+ vs_num++;
+
+ set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
+ user_sgpr_idx += vs_num;
+
ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
- ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
+ if (ctx->shader_info->info.vs.needs_draw_id)
+ ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
}
if (ctx->options->key.vs.as_es)
ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
}
+ if (ctx->options->key.vs.as_ls)
+ declare_tess_lds(ctx);
break;
case MESA_SHADER_TESS_CTRL:
set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
+
+ declare_tess_lds(ctx);
break;
case MESA_SHADER_TESS_EVAL:
set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
break;
case MESA_SHADER_FRAGMENT:
- set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
- user_sgpr_idx += 2;
- ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
+ if (ctx->shader_info->info.ps.needs_sample_positions) {
+ set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
+ user_sgpr_idx += 1;
+ ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
+ }
ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
}
+static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
+ LLVMValueRef src0)
+{
+ LLVMValueRef result;
+ LLVMValueRef cond;
+
+ src0 = to_float(ctx, src0);
+ result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
+
+ /* TODO SI/CIK options here */
+ if (ctx->options->chip_class >= VI) {
+ LLVMValueRef args[2];
+ /* Check if the result is a denormal - and flush to 0 if so. */
+ args[0] = result;
+ args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
+ cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
+ }
+
+ /* need to convert back up to f32 */
+ result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
+
+ if (ctx->options->chip_class >= VI)
+ result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
+
+ return result;
+}
+
static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
LLVMValueRef src0, LLVMValueRef src1)
{
case nir_op_fmax:
result = emit_intrin_2f_param(ctx, "llvm.maxnum",
to_float_type(ctx, def_type), src[0], src[1]);
+ if (instr->dest.dest.ssa.bit_size == 32)
+ result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
+ to_float_type(ctx, def_type),
+ result);
break;
case nir_op_fmin:
result = emit_intrin_2f_param(ctx, "llvm.minnum",
to_float_type(ctx, def_type), src[0], src[1]);
+ if (instr->dest.dest.ssa.bit_size == 32)
+ result = emit_intrin_1f_param(ctx, "llvm.canonicalize",
+ to_float_type(ctx, def_type),
+ result);
break;
case nir_op_ffma:
result = emit_intrin_3f_param(ctx, "llvm.fma",
result = emit_b2f(ctx, src[0]);
break;
case nir_op_fquantize2f16:
- src[0] = to_float(ctx, src[0]);
- result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
- /* need to convert back up to f32 */
- result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
+ result = emit_f2f16(ctx, src[0]);
break;
case nir_op_umul_high:
result = emit_umul_high(ctx, src[0], src[1]);
static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
nir_tex_instr *instr,
+ bool lod_is_zero,
struct ac_image_args *args)
{
if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
args->bias = true;
break;
case nir_texop_txl:
- args->lod = true;
+ if (lod_is_zero)
+ args->level_zero = true;
+ else
+ args->lod = true;
break;
case nir_texop_txs:
case nir_texop_query_levels:
is_compact, vertex_index, indir_index);
result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
- buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
+ buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
result = trim_vector(ctx, result, instr->num_components);
result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
return result;
static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
LLVMValueRef sample_id)
{
- /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
- LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
- LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
- LLVMValueRef result[2];
+ LLVMValueRef result;
+ LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
- result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
- result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
+ ptr = LLVMBuildBitCast(ctx->builder, ptr,
+ const_array(ctx->v2f32, 64), "");
- return ac_build_gather_values(&ctx->ac, result, 2);
+ sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
+ result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
+
+ return result;
}
static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
location = INTERP_CENTROID;
break;
case nir_intrinsic_interp_var_at_sample:
- location = INTERP_SAMPLE;
- src0 = get_src(ctx, instr->src[0]);
- break;
case nir_intrinsic_interp_var_at_offset:
location = INTERP_CENTER;
src0 = get_src(ctx, instr->src[0]);
+ break;
default:
break;
}
constant_index = child->base_offset;
}
- if (desc_type == DESC_SAMPLER && binding->immutable_samplers &&
+ if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
(!index || binding->immutable_samplers_equal)) {
if (binding->immutable_samplers_equal)
constant_index = 0;
+ const uint32_t *samplers = radv_immutable_samplers(layout, binding);
+
LLVMValueRef constants[] = {
- LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 0], 0),
- LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 1], 0),
- LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 2], 0),
- LLVMConstInt(ctx->i32, binding->immutable_samplers[constant_index * 4 + 3], 0),
+ LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
+ LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
+ LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
+ LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
};
return ac_build_gather_values(&ctx->ac, constants, 4);
}
LLVMValueRef derivs[6];
unsigned chan, count = 0;
unsigned const_src = 0, num_deriv_comp = 0;
-
+ bool lod_is_zero = false;
tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
for (unsigned i = 0; i < instr->num_srcs; i++) {
case nir_tex_src_bias:
bias = get_src(ctx, instr->src[i].src);
break;
- case nir_tex_src_lod:
+ case nir_tex_src_lod: {
+ nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
+
+ if (val && val->i32[0] == 0)
+ lod_is_zero = true;
lod = get_src(ctx, instr->src[i].src);
break;
+ }
case nir_tex_src_ms_index:
sample_index = get_src(ctx, instr->src[i].src);
break;
}
for (unsigned i = 0; i < num_deriv_comp; i++) {
- derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
- derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
+ derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
+ derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
}
}
if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
+ if (instr->is_array && instr->op != nir_texop_lod)
+ coords[3] = apply_round_slice(ctx, coords[3]);
for (chan = 0; chan < instr->coord_components; chan++)
coords[chan] = to_float(ctx, coords[chan]);
if (instr->coord_components == 3)
}
if (instr->coord_components > 2) {
/* This seems like a bit of a hack - but it passes Vulkan CTS with it */
- if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
+ if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
+ instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
+ instr->op != nir_texop_txf) {
coords[2] = apply_round_slice(ctx, coords[2]);
}
address[count++] = coords[2];
}
/* Pack LOD */
- if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
+ if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
+ instr->op == nir_texop_txf)) {
address[count++] = lod;
} else if (instr->op == nir_texop_txf_ms && sample_index) {
address[count++] = sample_index;
fmask_ptr, NULL,
txf_address, txf_count, 0xf);
- result = build_tex_intrinsic(ctx, instr, &txf_args);
+ result = build_tex_intrinsic(ctx, instr, false, &txf_args);
result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
set_tex_fetch_args(ctx, &args, instr, instr->op,
res_ptr, samp_ptr, address, count, dmask);
- result = build_tex_intrinsic(ctx, instr, &args);
+ result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
if (instr->op == nir_texop_query_levels)
result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
LLVMValueRef t_list_ptr = ctx->vertex_buffers;
LLVMValueRef t_offset;
LLVMValueRef t_list;
- LLVMValueRef args[3];
LLVMValueRef input;
LLVMValueRef buffer_index;
int index = variable->data.location - VERT_ATTRIB_GENERIC0;
t_offset = LLVMConstInt(ctx->i32, index + i, false);
t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
- args[0] = t_list;
- args[1] = LLVMConstInt(ctx->i32, 0, false);
- args[2] = buffer_index;
- input = ac_build_intrinsic(&ctx->ac,
- "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
- AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND |
- AC_FUNC_ATTR_LEGACY);
+
+ input = ac_build_buffer_load_format(&ctx->ac, t_list,
+ buffer_index,
+ LLVMConstInt(ctx->i32, 0, false),
+ true);
for (unsigned chan = 0; chan < 4; chan++) {
LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
int i;
- outinfo->prim_id_output = 0xffffffff;
- outinfo->layer_output = 0xffffffff;
+ memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
+ sizeof(outinfo->vs_output_param_offset));
+
if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
LLVMValueRef slots[8];
unsigned j;
} else if (i == VARYING_SLOT_LAYER) {
outinfo->writes_layer = true;
layer_value = values[0];
- outinfo->layer_output = param_count;
target = V_008DFC_SQ_EXP_PARAM + param_count;
+ outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
param_count++;
} else if (i == VARYING_SLOT_VIEWPORT) {
outinfo->writes_viewport_index = true;
viewport_index_value = values[0];
continue;
} else if (i == VARYING_SLOT_PRIMITIVE_ID) {
- outinfo->prim_id_output = param_count;
target = V_008DFC_SQ_EXP_PARAM + param_count;
+ outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
param_count++;
} else if (i >= VARYING_SLOT_VAR0) {
outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
target = V_008DFC_SQ_EXP_PARAM + param_count;
+ outinfo->vs_output_param_offset[i] = param_count;
param_count++;
}
write_tess_factors(ctx);
}
-static void
+static bool
si_export_mrt_color(struct nir_to_llvm_context *ctx,
- LLVMValueRef *color, unsigned param, bool is_last)
+ LLVMValueRef *color, unsigned param, bool is_last,
+ struct ac_export_args *args)
{
-
- struct ac_export_args args;
-
/* Export */
si_llvm_init_export_args(ctx, color, param,
- &args);
+ args);
if (is_last) {
- args.valid_mask = 1; /* whether the EXEC mask is valid */
- args.done = 1; /* DONE bit */
- } else if (!args.enabled_channels)
- return; /* unnecessary NULL export */
+ args->valid_mask = 1; /* whether the EXEC mask is valid */
+ args->done = 1; /* DONE bit */
+ } else if (!args->enabled_channels)
+ return false; /* unnecessary NULL export */
- ac_build_export(&ctx->ac, &args);
+ return true;
}
static void
{
unsigned index = 0;
LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
+ struct ac_export_args color_args[8];
for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef values[4];
if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
- si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
- index++;
+ bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
+ if (ret)
+ index++;
}
}
+ for (unsigned i = 0; i < index; i++)
+ ac_build_export(&ctx->ac, &color_args[i]);
if (depth || stencil || samplemask)
si_export_mrt_z(ctx, depth, stencil, samplemask);
- else if (!index)
- si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
+ else if (!index) {
+ si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
+ ac_build_export(&ctx->ac, &color_args[0]);
+ }
ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
}
LLVMDisposePassManager(passmgr);
}
+static void
+ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
+{
+ struct ac_vs_output_info *outinfo;
+
+ if (ctx->stage == MESA_SHADER_FRAGMENT ||
+ ctx->stage == MESA_SHADER_COMPUTE ||
+ ctx->stage == MESA_SHADER_TESS_CTRL ||
+ ctx->stage == MESA_SHADER_GEOMETRY)
+ return;
+
+ if (ctx->stage == MESA_SHADER_VERTEX) {
+ if (ctx->options->key.vs.as_ls ||
+ ctx->options->key.vs.as_es)
+ return;
+ outinfo = &ctx->shader_info->vs.outinfo;
+ }
+
+ if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+ if (ctx->options->key.vs.as_es)
+ return;
+ outinfo = &ctx->shader_info->tes.outinfo;
+ }
+
+ ac_optimize_vs_outputs(&ctx->ac,
+ ctx->main_function,
+ outinfo->vs_output_param_offset,
+ VARYING_SLOT_MAX,
+ &outinfo->param_exports);
+}
+
static void
ac_setup_rings(struct nir_to_llvm_context *ctx)
{
}
}
+static unsigned
+ac_nir_get_max_workgroup_size(enum chip_class chip_class,
+ struct nir_shader *nir)
+{
+ switch (nir->stage) {
+ case MESA_SHADER_TESS_CTRL:
+ return chip_class >= CIK ? 128 : 64;
+ case MESA_SHADER_GEOMETRY:
+ return 64;
+ case MESA_SHADER_COMPUTE:
+ break;
+ default:
+ return 0;
+ }
+
+ unsigned max_workgroup_size = nir->info.cs.local_size[0] *
+ nir->info.cs.local_size[1] *
+ nir->info.cs.local_size[2];
+ return max_workgroup_size;
+}
+
static
LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
struct nir_shader *nir,
memset(shader_info, 0, sizeof(*shader_info));
+ ac_nir_shader_info_pass(nir, options, &shader_info->info);
+
LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
ctx.builder = LLVMCreateBuilderInContext(ctx.context);
ctx.ac.builder = ctx.builder;
ctx.stage = nir->stage;
+ ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
for (i = 0; i < AC_UD_MAX_SETS; i++)
shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
} else if (nir->stage == MESA_SHADER_GEOMETRY) {
ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
- ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
+ ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
} else if (nir->stage == MESA_SHADER_TESS_EVAL) {
- ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
+ ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
}
ac_setup_rings(&ctx);
if (nir->stage == MESA_SHADER_FRAGMENT)
handle_fs_inputs_pre(&ctx, nir);
- ctx.num_output_clips = nir->info->clip_distance_array_size;
- ctx.num_output_culls = nir->info->cull_distance_array_size;
+ ctx.num_output_clips = nir->info.clip_distance_array_size;
+ ctx.num_output_culls = nir->info.cull_distance_array_size;
nir_foreach_variable(variable, &nir->outputs)
handle_shader_output_decl(&ctx, variable);
LLVMBuildRetVoid(ctx.builder);
ac_llvm_finalize_module(&ctx);
+
+ ac_nir_eliminate_const_vs_outputs(&ctx);
free(ctx.locals);
ralloc_free(ctx.defs);
ralloc_free(ctx.phis);
unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
- nir->info->gs.vertices_out;
+ nir->info.gs.vertices_out;
} else if (nir->stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.outputs_written = ctx.tess_outputs_written;
shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
switch (nir->stage) {
case MESA_SHADER_COMPUTE:
for (int i = 0; i < 3; ++i)
- shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
+ shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
break;
case MESA_SHADER_FRAGMENT:
- shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
+ shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
break;
case MESA_SHADER_GEOMETRY:
- shader_info->gs.vertices_in = nir->info->gs.vertices_in;
- shader_info->gs.vertices_out = nir->info->gs.vertices_out;
- shader_info->gs.output_prim = nir->info->gs.output_primitive;
- shader_info->gs.invocations = nir->info->gs.invocations;
+ shader_info->gs.vertices_in = nir->info.gs.vertices_in;
+ shader_info->gs.vertices_out = nir->info.gs.vertices_out;
+ shader_info->gs.output_prim = nir->info.gs.output_primitive;
+ shader_info->gs.invocations = nir->info.gs.invocations;
break;
case MESA_SHADER_TESS_EVAL:
- shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
- shader_info->tes.spacing = nir->info->tess.spacing;
- shader_info->tes.ccw = nir->info->tess.ccw;
- shader_info->tes.point_mode = nir->info->tess.point_mode;
+ shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
+ shader_info->tes.spacing = nir->info.tess.spacing;
+ shader_info->tes.ccw = nir->info.tess.ccw;
+ shader_info->tes.point_mode = nir->info.tess.point_mode;
shader_info->tes.as_es = options->key.tes.as_es;
break;
case MESA_SHADER_TESS_CTRL:
- shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
+ shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
break;
case MESA_SHADER_VERTEX:
shader_info->vs.as_es = options->key.vs.as_es;
create_function(&ctx);
- ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
+ ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
ac_setup_rings(&ctx);
- ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
- ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
+ ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
+ ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
nir_foreach_variable(variable, &geom_shader->outputs)
handle_shader_output_decl(&ctx, variable);
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