if (num_bytes == 1) {
ac_build_tbuffer_store_byte(&ctx->ac, rsrc, data,
offset, ctx->ac.i32_0,
- cache_policy & ac_glc,
- writeonly_memory);
+ cache_policy & ac_glc);
} else if (num_bytes == 2) {
ac_build_tbuffer_store_short(&ctx->ac, rsrc, data,
offset, ctx->ac.i32_0,
- cache_policy & ac_glc,
- writeonly_memory);
+ cache_policy & ac_glc);
} else {
int num_channels = num_bytes / 4;
num_channels, offset,
ctx->ac.i32_0, 0,
cache_policy & ac_glc,
- false, writeonly_memory,
- false);
+ false, false);
}
}
}
cache_policy & ac_glc);
} else {
int num_channels = util_next_power_of_two(load_bytes) / 4;
+ bool can_speculate = access & ACCESS_CAN_REORDER;
ret = ac_build_buffer_load(&ctx->ac, rsrc, num_channels,
vindex, offset, immoffset, 0,
cache_policy & ac_glc, 0,
- false, false);
+ can_speculate, false);
}
LLVMTypeRef byte_vec = LLVMVectorType(ctx->ac.i8, ac_get_type_size(LLVMTypeOf(ret)));
vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[1]),
ctx->ac.i32_0, "");
- /* TODO: set "can_speculate" when OpenGL needs it. */
+ bool can_speculate = access & ACCESS_CAN_REORDER;
res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
ctx->ac.i32_0, num_channels,
!!(args.cache_policy & ac_glc),
- false);
+ can_speculate);
res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
res = ac_trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
ac_build_buffer_store_format(&ctx->ac, rsrc, src, vindex,
ctx->ac.i32_0, src_channels,
- args.cache_policy & ac_glc,
- writeonly_memory);
+ args.cache_policy & ac_glc, false);
} else {
args.opcode = ac_image_store;
args.data[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[3]));
case nir_intrinsic_quad_swap_diagonal:
result = ac_build_quad_swizzle(&ctx->ac, get_src(ctx, instr->src[0]), 3, 2, 1 ,0);
break;
+ case nir_intrinsic_quad_swizzle_amd: {
+ uint32_t mask = nir_intrinsic_swizzle_mask(instr);
+ result = ac_build_quad_swizzle(&ctx->ac, get_src(ctx, instr->src[0]),
+ mask & 0x3, (mask >> 2) & 0x3,
+ (mask >> 4) & 0x3, (mask >> 6) & 0x3);
+ break;
+ }
+ case nir_intrinsic_masked_swizzle_amd: {
+ uint32_t mask = nir_intrinsic_swizzle_mask(instr);
+ result = ac_build_ds_swizzle(&ctx->ac, get_src(ctx, instr->src[0]), mask);
+ break;
+ }
+ case nir_intrinsic_write_invocation_amd:
+ result = ac_build_writelane(&ctx->ac, get_src(ctx, instr->src[0]),
+ get_src(ctx, instr->src[1]),
+ get_src(ctx, instr->src[2]));
+ break;
+ case nir_intrinsic_mbcnt_amd:
+ result = ac_build_mbcnt(&ctx->ac, get_src(ctx, instr->src[0]));
+ break;
default:
fprintf(stderr, "Unknown intrinsic: ");
nir_print_instr(&instr->instr, stderr);
args.offset = NULL;
}
- /* TODO TG4 support */
+ /* DMASK was repurposed for GATHER4. 4 components are always
+ * returned and DMASK works like a swizzle - it selects
+ * the component to fetch. The only valid DMASK values are
+ * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
+ * (red,red,red,red) etc.) The ISA document doesn't mention
+ * this.
+ */
args.dmask = 0xf;
if (instr->op == nir_texop_tg4) {
if (instr->is_shadow)