radv/ac: propogate as_es flag into shader info from key.

[mesa.git] / src / amd / common / ac_nir_to_llvm.h

diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index ca06d059a6d0d09fc1c43d15c58e2b64daa3bd88..783331160e556b35f80d2e9f90375bd98aa03b0a 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -36,6 +36,7 @@ struct radv_pipeline_layout;
 
 struct ac_vs_variant_key {
        uint32_t instance_rate_inputs;
+       uint32_t as_es:1;
 };
 
 struct ac_fs_variant_key {
@@ -52,11 +53,43 @@ struct ac_nir_compiler_options {
        struct radv_pipeline_layout *layout;
        union ac_shader_variant_key key;
        bool unsafe_math;
+       bool supports_spill;
        enum radeon_family family;
        enum chip_class chip_class;
 };
 
+struct ac_userdata_info {
+       int8_t sgpr_idx;
+       uint8_t num_sgprs;
+       bool indirect;
+       uint32_t indirect_offset;
+};
+
+enum ac_ud_index {
+       AC_UD_SCRATCH_RING_OFFSETS = 0,
+       AC_UD_PUSH_CONSTANTS = 1,
+       AC_UD_SHADER_START = 2,
+       AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
+       AC_UD_VS_BASE_VERTEX_START_INSTANCE,
+       AC_UD_VS_MAX_UD,
+       AC_UD_PS_SAMPLE_POS = AC_UD_SHADER_START,
+       AC_UD_PS_MAX_UD,
+       AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
+       AC_UD_CS_MAX_UD,
+       AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_SHADER_START,
+       AC_UD_GS_MAX_UD,
+       AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
+};
+
+#define AC_UD_MAX_SETS 4
+
+struct ac_userdata_locations {
+       struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
+       struct ac_userdata_info shader_data[AC_UD_MAX_UD];
+};
+
 struct ac_shader_variant_info {
+       struct ac_userdata_locations user_sgprs_locs;
        unsigned num_user_sgprs;
        unsigned num_input_sgprs;
        unsigned num_input_vgprs;
@@ -67,6 +100,9 @@ struct ac_shader_variant_info {
                        unsigned vgpr_comp_cnt;
                        uint32_t export_mask;
                        bool writes_pointsize;
+                       bool writes_layer;
+                       bool writes_viewport_index;
+                       bool as_es;
                        uint8_t clip_dist_mask;
                        uint8_t cull_dist_mask;
                } vs;
@@ -81,10 +117,17 @@ struct ac_shader_variant_info {
                        bool writes_stencil;
                        bool early_fragment_test;
                        bool writes_memory;
+                       bool force_persample;
                } fs;
                struct {
                        unsigned block_size[3];
                } cs;
+               struct {
+                       unsigned vertices_in;
+                       unsigned vertices_out;
+                       unsigned output_prim;
+                       unsigned invocations;
+               } gs;
        };
 };
 
@@ -96,20 +139,4 @@ void ac_compile_nir_shader(LLVMTargetMachineRef tm,
                            const struct ac_nir_compiler_options *options,
                           bool dump_shader);
 
-/* SHADER ABI defines */
-
-/* offset in dwords */
-#define AC_USERDATA_DESCRIPTOR_SET_0 0
-#define AC_USERDATA_DESCRIPTOR_SET_1 2
-#define AC_USERDATA_DESCRIPTOR_SET_2 4
-#define AC_USERDATA_DESCRIPTOR_SET_3 6
-#define AC_USERDATA_PUSH_CONST_DYN 8
-
-#define AC_USERDATA_VS_VERTEX_BUFFERS 10
-#define AC_USERDATA_VS_BASE_VERTEX 12
-#define AC_USERDATA_VS_START_INSTANCE 13
-
-#define AC_USERDATA_PS_SAMPLE_POS 10
-
-#define AC_USERDATA_CS_GRID_SIZE 10