*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
break;
+ case CHIP_VEGA12:
+ *addrlib_family = FAMILY_AI;
+ *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
+ break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
- ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
+ ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
}
static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
+ const struct ac_surf_config *config,
struct radeon_surf *surf, bool compressed,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
{
hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
- hin.hTileFlags.pipeAligned = 1;
- hin.hTileFlags.rbAligned = 1;
+ hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
+ hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
hin.depthFlags = in->flags;
hin.swizzleMode = in->swizzleMode;
hin.unalignedWidth = in->width;
surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
} else {
+ /* Compute tile swizzle for the color surface.
+ * All *_X and *_T modes can use the swizzle.
+ */
+ if (config->info.surf_index &&
+ in->swizzleMode >= ADDR_SW_64KB_Z_T &&
+ !out.mipChainInTail &&
+ !(surf->flags & RADEON_SURF_SHAREABLE) &&
+ (in->numSamples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
+ ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
+ ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
+
+ xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
+ xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
+
+ xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
+ xin.flags = in->flags;
+ xin.swizzleMode = in->swizzleMode;
+ xin.resourceType = in->resourceType;
+ xin.format = in->format;
+ xin.numSamples = in->numSamples;
+ xin.numFrags = in->numFrags;
+
+ ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
+ if (ret != ADDR_OK)
+ return ret;
+
+ assert(xout.pipeBankXor <=
+ u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
+ surf->tile_swizzle = xout.pipeBankXor;
+ }
+
/* DCC */
if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
- !(surf->flags & RADEON_SURF_SCANOUT) &&
!compressed &&
in->swizzleMode != ADDR_SW_LINEAR) {
ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
dout.pMipInfo = meta_mip_info;
- din.dccKeyFlags.pipeAligned = 1;
- din.dccKeyFlags.rbAligned = 1;
+ din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
+ din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
din.colorFlags = in->flags;
din.resourceType = in->resourceType;
din.swizzleMode = in->swizzleMode;
surf->u.gfx9.fmask.epitch = fout.pitch - 1;
surf->u.gfx9.fmask_size = fout.fmaskBytes;
surf->u.gfx9.fmask_alignment = fout.baseAlign;
+
+ /* Compute tile swizzle for the FMASK surface. */
+ if (config->info.fmask_surf_index &&
+ fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
+ !(surf->flags & RADEON_SURF_SHAREABLE)) {
+ ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
+ ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
+
+ xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
+ xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
+
+ /* This counter starts from 1 instead of 0. */
+ xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
+ xin.flags = in->flags;
+ xin.swizzleMode = in->swizzleMode;
+ xin.resourceType = in->resourceType;
+ xin.format = in->format;
+ xin.numSamples = in->numSamples;
+ xin.numFrags = in->numFrags;
+
+ ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
+ if (ret != ADDR_OK)
+ return ret;
+
+ assert(xout.pipeBankXor <=
+ u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
+ surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
+ }
}
/* CMASK */
cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
- cin.cMaskFlags.pipeAligned = 1;
- cin.cMaskFlags.rbAligned = 1;
+ if (in->numSamples) {
+ /* FMASK is always aligned. */
+ cin.cMaskFlags.pipeAligned = 1;
+ cin.cMaskFlags.rbAligned = 1;
+ } else {
+ cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
+ cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
+ }
cin.colorFlags = in->flags;
cin.resourceType = in->resourceType;
cin.unalignedWidth = in->width;
}
static int gfx9_compute_surface(ADDR_HANDLE addrlib,
+ const struct radeon_info *info,
const struct ac_surf_config *config,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
assert(0);
}
} else {
+ switch (surf->bpe) {
+ case 1:
+ assert(!(surf->flags & RADEON_SURF_ZBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_8;
+ break;
+ case 2:
+ assert(surf->flags & RADEON_SURF_ZBUFFER ||
+ !(surf->flags & RADEON_SURF_SBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_16;
+ break;
+ case 4:
+ assert(surf->flags & RADEON_SURF_ZBUFFER ||
+ !(surf->flags & RADEON_SURF_SBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_32;
+ break;
+ case 8:
+ assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_32_32;
+ break;
+ case 16:
+ assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
+ break;
+ default:
+ assert(0);
+ }
AddrSurfInfoIn.bpp = surf->bpe * 8;
}
else
AddrSurfInfoIn.numSlices = config->info.array_size;
+ /* This is propagated to HTILE/DCC/CMASK. */
+ AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
+ AddrSurfInfoIn.flags.metaRbUnaligned = 0;
+
switch (mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
assert(config->info.samples <= 1);
surf->u.gfx9.cmask_size = 0;
/* Calculate texture layout information. */
- r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
+ r = gfx9_compute_miptree(addrlib, config, surf, compressed,
+ &AddrSurfInfoIn);
if (r)
return r;
if (surf->flags & RADEON_SURF_SBUFFER) {
AddrSurfInfoIn.flags.stencil = 1;
AddrSurfInfoIn.bpp = 8;
+ AddrSurfInfoIn.format = ADDR_FMT_8;
if (!AddrSurfInfoIn.flags.depth) {
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
} else
AddrSurfInfoIn.flags.depth = 0;
- r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
+ r = gfx9_compute_miptree(addrlib, config, surf, compressed,
+ &AddrSurfInfoIn);
if (r)
return r;
}
assert(0);
}
+ /* Temporary workaround to prevent VM faults and hangs. */
+ if (info->family == CHIP_VEGA12)
+ surf->u.gfx9.fmask_size *= 8;
+
return 0;
}
return r;
if (info->chip_class >= GFX9)
- return gfx9_compute_surface(addrlib, config, mode, surf);
+ return gfx9_compute_surface(addrlib, info, config, mode, surf);
else
return gfx6_compute_surface(addrlib, info, config, mode, surf);
}
projects / mesa.git / blobdiff