Revert "amd/common: Always initialize gfx9 mipmap offset/pitch."

[mesa.git] / src / amd / common / ac_surface.c

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 81c77e280ae0732f526090de436480d30b402e76..92aab57920a35feda4c678389f177c3f63a74aeb 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -206,6 +206,17 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
                AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
        }
 
+       /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
+        * true for r32g32b32 formats. */
+       if (AddrSurfInfoIn->bpp == 96) {
+               assert(config->info.levels == 1);
+               assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
+
+               /* The least common multiple of 64 bytes and 12 bytes/pixel is
+                * 192 bytes, or 16 pixels. */
+               AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
+       }
+
        if (config->is_3d)
                AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
        else if (config->is_cube)
@@ -1051,8 +1062,10 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
        surf->surf_alignment = out.baseAlign;
 
        if (in->swizzleMode == ADDR_SW_LINEAR) {
-               for (unsigned i = 0; i < in->numMipLevels; i++)
+               for (unsigned i = 0; i < in->numMipLevels; i++) {
                        surf->u.gfx9.offset[i] = mip_info[i].offset;
+                       surf->u.gfx9.pitch[i] = mip_info[i].pitch;
+               }
        }
 
        if (in->flags.depth) {