if (addrCreateInput.chipFamily >= FAMILY_AI) {
addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
- regValue.blockVarSizeLog2 = 0;
} else {
regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
}
+ /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
+ * true for r32g32b32 formats. */
+ if (AddrSurfInfoIn->bpp == 96) {
+ assert(config->info.levels == 1);
+ assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
+
+ /* The least common multiple of 64 bytes and 12 bytes/pixel is
+ * 192 bytes, or 16 pixels. */
+ AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
+ }
+
if (config->is_3d)
AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
else if (config->is_cube)
}
}
- /* TC-compatible HTILE. */
+ /* HTILE. */
if (!is_stencil &&
AddrSurfInfoIn->flags.depth &&
surf_level->mode == RADEON_SURF_MODE_2D &&
- level == 0) {
- AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
+ level == 0 &&
+ !(surf->flags & RADEON_SURF_NO_HTILE)) {
+ AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
AddrHtileIn->height = AddrSurfInfoOut->height;
AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
unsigned num_pipes = info->num_tile_pipes;
unsigned cl_width, cl_height;
- if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
+ if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
+ (config->info.samples >= 2 && !surf->fmask_size))
return;
assert(info->chip_class <= GFX8);
if (level > 0)
continue;
- /* Check that we actually got a TC-compatible HTILE if
- * we requested it (only for level 0, since we're not
- * supporting HTILE on higher mip levels anyway). */
- assert(AddrSurfInfoOut.tcCompatible ||
- !AddrSurfInfoIn.flags.tcCompatible ||
- AddrSurfInfoIn.flags.matchStencilTileCfg);
+ if (!AddrSurfInfoOut.tcCompatible) {
+ AddrSurfInfoIn.flags.tcCompatible = 0;
+ surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
+ }
if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
- if (!AddrSurfInfoOut.tcCompatible) {
- AddrSurfInfoIn.flags.tcCompatible = 0;
- surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
- }
-
AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
}
/* Compute FMASK. */
- if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
+ if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
+ info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
ADDR_TILEINFO fmask_tile_info = {};
surf->surf_alignment = out.baseAlign;
if (in->swizzleMode == ADDR_SW_LINEAR) {
- for (unsigned i = 0; i < in->numMipLevels; i++)
+ for (unsigned i = 0; i < in->numMipLevels; i++) {
surf->u.gfx9.offset[i] = mip_info[i].offset;
+ surf->u.gfx9.pitch[i] = mip_info[i].pitch;
+ }
}
if (in->flags.depth) {
assert(in->swizzleMode != ADDR_SW_LINEAR);
+ if (surf->flags & RADEON_SURF_NO_HTILE)
+ return 0;
+
/* HTILE */
ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
surf->htile_size = hout.htileBytes;
surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
- } else {
+ return 0;
+ }
+
+ {
/* Compute tile swizzle for the color surface.
* All *_X and *_T modes can use the swizzle.
*/
return ret;
surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
- if (addrout.addr > USHRT_MAX)
+ if (addrout.addr > UINT16_MAX)
surf->u.gfx9.dcc_retile_use_uint16 = false;
/* Compute dst DCC address */
return ret;
surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
- if (addrout.addr > USHRT_MAX)
+ if (addrout.addr > UINT16_MAX)
surf->u.gfx9.dcc_retile_use_uint16 = false;
assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
}
/* FMASK */
- if (in->numSamples > 1) {
+ if (in->numSamples > 1 && info->has_graphics &&
+ !(surf->flags & RADEON_SURF_NO_FMASK)) {
ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
/* CMASK -- on GFX10 only for FMASK */
if (in->swizzleMode != ADDR_SW_LINEAR &&
- (info->chip_class <= GFX9 || in->numSamples > 1)) {
+ in->resourceType == ADDR_RSRC_TEX_2D &&
+ ((info->chip_class <= GFX9 && in->numSamples == 1) ||
+ (surf->fmask_size && in->numSamples >= 2))) {
ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
case ADDR_SW_256B_S:
case ADDR_SW_4KB_S:
case ADDR_SW_64KB_S:
- case ADDR_SW_VAR_S:
case ADDR_SW_64KB_S_T:
case ADDR_SW_4KB_S_X:
case ADDR_SW_64KB_S_X:
- case ADDR_SW_VAR_S_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
break;
case ADDR_SW_256B_D:
case ADDR_SW_4KB_D:
case ADDR_SW_64KB_D:
- case ADDR_SW_VAR_D:
case ADDR_SW_64KB_D_T:
case ADDR_SW_4KB_D_X:
case ADDR_SW_64KB_D_X:
- case ADDR_SW_VAR_D_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
break;
case ADDR_SW_256B_R:
case ADDR_SW_4KB_R:
case ADDR_SW_64KB_R:
- case ADDR_SW_VAR_R:
case ADDR_SW_64KB_R_T:
case ADDR_SW_4KB_R_X:
case ADDR_SW_64KB_R_X:
/* Z = depth. */
case ADDR_SW_4KB_Z:
case ADDR_SW_64KB_Z:
- case ADDR_SW_VAR_Z:
case ADDR_SW_64KB_Z_T:
case ADDR_SW_4KB_Z_X:
case ADDR_SW_64KB_Z_X:
return r;
if (info->chip_class >= GFX9)
- return gfx9_compute_surface(addrlib, info, config, mode, surf);
+ r = gfx9_compute_surface(addrlib, info, config, mode, surf);
else
- return gfx6_compute_surface(addrlib, info, config, mode, surf);
+ r = gfx6_compute_surface(addrlib, info, config, mode, surf);
+
+ if (r)
+ return r;
+
+ /* Determine the memory layout of multiple allocations in one buffer. */
+ surf->total_size = surf->surf_size;
+
+ if (surf->htile_size) {
+ surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
+ surf->total_size = surf->htile_offset + surf->htile_size;
+ }
+
+ if (surf->fmask_size) {
+ assert(config->info.samples >= 2);
+ surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
+ surf->total_size = surf->fmask_offset + surf->fmask_size;
+ }
+
+ /* Single-sample CMASK is in a separate buffer. */
+ if (surf->cmask_size && config->info.samples >= 2) {
+ surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
+ surf->total_size = surf->cmask_offset + surf->cmask_size;
+ }
+
+ if (surf->dcc_size &&
+ (info->use_display_dcc_unaligned ||
+ info->use_display_dcc_with_retile_blit ||
+ !(surf->flags & RADEON_SURF_SCANOUT))) {
+ surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
+ surf->total_size = surf->dcc_offset + surf->dcc_size;
+
+ if (info->chip_class >= GFX9 &&
+ surf->u.gfx9.dcc_retile_num_elements) {
+ /* Add space for the displayable DCC buffer. */
+ surf->display_dcc_offset =
+ align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
+ surf->total_size = surf->display_dcc_offset +
+ surf->u.gfx9.display_dcc_size;
+
+ /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
+ surf->dcc_retile_map_offset =
+ align64(surf->total_size, info->tcc_cache_line_size);
+
+ if (surf->u.gfx9.dcc_retile_use_uint16) {
+ surf->total_size = surf->dcc_retile_map_offset +
+ surf->u.gfx9.dcc_retile_num_elements * 2;
+ } else {
+ surf->total_size = surf->dcc_retile_map_offset +
+ surf->u.gfx9.dcc_retile_num_elements * 4;
+ }
+ }
+ }
+
+ return 0;
}
projects / mesa.git / blobdiff