#include "ac_surface.h"
#include "amd_family.h"
-#include "addrlib/amdgpu_asic_addr.h"
+#include "addrlib/src/amdgpu_asic_addr.h"
#include "ac_gpu_info.h"
#include "util/macros.h"
#include "util/u_atomic.h"
#include <amdgpu.h>
#include <amdgpu_drm.h>
-#include "addrlib/addrinterface.h"
+#include "addrlib/inc/addrinterface.h"
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
break;
+ case CHIP_VEGA20:
+ *addrlib_family = FAMILY_AI;
+ *addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
+ break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
break;
+ case CHIP_RAVEN2:
+ *addrlib_family = FAMILY_RV;
+ *addrlib_revid = get_first(AMDGPU_RAVEN2_RANGE);
+ break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
}
return addrCreateOutput.hLib;
}
-static int surf_config_sanity(const struct ac_surf_config *config)
+static int surf_config_sanity(const struct ac_surf_config *config,
+ unsigned flags)
{
+ /* FMASK is allocated together with the color surface and can't be
+ * allocated separately.
+ */
+ assert(!(flags & RADEON_SURF_FMASK));
+ if (flags & RADEON_SURF_FMASK)
+ return -EINVAL;
+
/* all dimension must be at least 1 ! */
if (!config->info.width || !config->info.height || !config->info.depth ||
!config->info.array_size || !config->info.levels)
case 4:
case 8:
break;
+ case 16:
+ if (flags & RADEON_SURF_Z_OR_SBUFFER)
+ return -EINVAL;
+ break;
default:
return -EINVAL;
}
+ if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
+ switch (config->info.storage_samples) {
+ case 0:
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
if (config->is_3d && config->info.array_size > 1)
return -EINVAL;
if (config->is_cube && config->info.depth > 1)
*/
if (config->info.levels == 1 &&
AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
- AddrSurfInfoIn->bpp) {
+ AddrSurfInfoIn->bpp &&
+ util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
- assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
}
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
+#define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
unsigned bpe = surf->bpe;
if (surf->flags & RADEON_SURF_SCANOUT &&
- !(surf->flags & RADEON_SURF_FMASK) &&
config->info.samples <= 1 &&
surf->blk_w <= 2 && surf->blk_h == 1) {
/* subsampled */
return 0;
}
+void ac_compute_cmask(const struct radeon_info *info,
+ const struct ac_surf_config *config,
+ struct radeon_surf *surf)
+{
+ unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
+ unsigned num_pipes = info->num_tile_pipes;
+ unsigned cl_width, cl_height;
+
+ if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
+ return;
+
+ assert(info->chip_class <= VI);
+
+ switch (num_pipes) {
+ case 2:
+ cl_width = 32;
+ cl_height = 16;
+ break;
+ case 4:
+ cl_width = 32;
+ cl_height = 32;
+ break;
+ case 8:
+ cl_width = 64;
+ cl_height = 32;
+ break;
+ case 16: /* Hawaii */
+ cl_width = 64;
+ cl_height = 64;
+ break;
+ default:
+ assert(0);
+ return;
+ }
+
+ unsigned base_align = num_pipes * pipe_interleave_bytes;
+
+ unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
+ unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
+ unsigned slice_elements = (width * height) / (8*8);
+
+ /* Each element of CMASK is a nibble. */
+ unsigned slice_bytes = slice_elements / 2;
+
+ surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
+ if (surf->u.legacy.cmask_slice_tile_max)
+ surf->u.legacy.cmask_slice_tile_max -= 1;
+
+ unsigned num_layers;
+ if (config->is_3d)
+ num_layers = config->info.depth;
+ else if (config->is_cube)
+ num_layers = 6;
+ else
+ num_layers = config->info.array_size;
+
+ surf->cmask_alignment = MAX2(256, base_align);
+ surf->cmask_size = align(slice_bytes, base_align) * num_layers;
+}
+
/**
* Fill in the tiling information in \p surf based on the given surface config.
*
compressed = surf->blk_w == 4 && surf->blk_h == 4;
- /* MSAA and FMASK require 2D tiling. */
- if (config->info.samples > 1 ||
- (surf->flags & RADEON_SURF_FMASK))
+ /* MSAA requires 2D tiling. */
+ if (config->info.samples > 1)
mode = RADEON_SURF_MODE_2D;
/* DB doesn't support linear layouts. */
}
AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
- config->info.samples ? config->info.samples : 1;
+ MAX2(1, config->info.samples);
AddrSurfInfoIn.tileIndex = -1;
+ if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
+ AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
+ MAX2(1, config->info.storage_samples);
+ }
+
/* Set the micro tile type. */
if (surf->flags & RADEON_SURF_SCANOUT)
AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
- else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
+ else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
else
AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
AddrSurfInfoIn.flags.cube = config->is_cube;
- AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
config->info.levels == 1);
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
- AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
+ AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
/* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
* for Z and stencil. This can cause a number of problems which we work
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
surf->u.legacy.bankw && surf->u.legacy.bankh &&
surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
- assert(!(surf->flags & RADEON_SURF_FMASK));
-
/* If any of these parameters are incorrect, the calculation
* will fail. */
AddrTileInfoIn.banks = surf->u.legacy.num_banks;
}
}
+ /* Compute FMASK. */
+ if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
+ ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
+ ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
+ ADDR_TILEINFO fmask_tile_info = {};
+
+ fin.size = sizeof(fin);
+ fout.size = sizeof(fout);
+
+ fin.tileMode = AddrSurfInfoOut.tileMode;
+ fin.pitch = AddrSurfInfoOut.pitch;
+ fin.height = config->info.height;
+ fin.numSlices = AddrSurfInfoIn.numSlices;
+ fin.numSamples = AddrSurfInfoIn.numSamples;
+ fin.numFrags = AddrSurfInfoIn.numFrags;
+ fin.tileIndex = -1;
+ fout.pTileInfo = &fmask_tile_info;
+
+ r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
+ if (r)
+ return r;
+
+ surf->fmask_size = fout.fmaskBytes;
+ surf->fmask_alignment = fout.baseAlign;
+ surf->fmask_tile_swizzle = 0;
+
+ surf->u.legacy.fmask.slice_tile_max =
+ (fout.pitch * fout.height) / 64;
+ if (surf->u.legacy.fmask.slice_tile_max)
+ surf->u.legacy.fmask.slice_tile_max -= 1;
+
+ surf->u.legacy.fmask.tiling_index = fout.tileIndex;
+ surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
+ surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
+
+ /* Compute tile swizzle for FMASK. */
+ if (config->info.fmask_surf_index &&
+ !(surf->flags & RADEON_SURF_SHAREABLE)) {
+ ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
+ ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
+
+ xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
+ xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
+
+ /* This counter starts from 1 instead of 0. */
+ xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
+ xin.tileIndex = fout.tileIndex;
+ xin.macroModeIndex = fout.macroModeIndex;
+ xin.pTileInfo = fout.pTileInfo;
+ xin.tileMode = fin.tileMode;
+
+ int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
+ if (r != ADDR_OK)
+ return r;
+
+ assert(xout.tileSwizzle <=
+ u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
+ surf->fmask_tile_swizzle = xout.tileSwizzle;
+ }
+ }
+
/* Recalculate the whole DCC miptree size including disabled levels.
* This is what addrlib does, but calling addrlib would be a lot more
* complicated.
/* Make sure HTILE covers the whole miptree, because the shader reads
* TC-compatible HTILE even for levels where it's disabled by DB.
*/
- if (surf->htile_size && config->info.levels > 1)
- surf->htile_size *= 2;
+ if (surf->htile_size && config->info.levels > 1 &&
+ surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
+ /* MSAA can't occur with levels > 1, so ignore the sample count. */
+ const unsigned total_pixels = surf->surf_size / surf->bpe;
+ const unsigned htile_block_size = 8 * 8;
+ const unsigned htile_element_size = 4;
+
+ surf->htile_size = (total_pixels / htile_block_size) *
+ htile_element_size;
+ surf->htile_size = align(surf->htile_size, surf->htile_alignment);
+ }
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
+
+ /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
+ * used at the same time. This case is not currently expected to occur
+ * because we don't use rotated. Enforce this restriction on all chips
+ * to facilitate testing.
+ */
+ if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
+ assert(!"rotate micro tile mode is unsupported");
+ return ADDR_ERROR;
+ }
+
+ ac_compute_cmask(info, config, surf);
return 0;
}
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
- bool is_fmask, unsigned flags,
- AddrSwizzleMode *swizzle_mode)
+ bool is_fmask, AddrSwizzleMode *swizzle_mode)
{
ADDR_E_RETURNCODE ret;
ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
sin.numSamples = in->numSamples;
sin.numFrags = in->numFrags;
- if (flags & RADEON_SURF_SCANOUT) {
- sin.preferredSwSet.sw_D = 1;
- /* Raven only allows S for displayable surfaces with < 64 bpp, so
- * allow it as fallback */
- sin.preferredSwSet.sw_S = 1;
- } else if (in->flags.depth || in->flags.stencil || is_fmask)
- sin.preferredSwSet.sw_Z = 1;
- else
- sin.preferredSwSet.sw_S = 1;
-
if (is_fmask) {
sin.flags.display = 0;
sin.flags.color = 0;
fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
- true, surf->flags,
- &fin.swizzleMode);
+ true, &fin.swizzleMode);
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
surf->u.gfx9.fmask.epitch = fout.pitch - 1;
- surf->u.gfx9.fmask_size = fout.fmaskBytes;
- surf->u.gfx9.fmask_alignment = fout.baseAlign;
+ surf->fmask_size = fout.fmaskBytes;
+ surf->fmask_alignment = fout.baseAlign;
/* Compute tile swizzle for the FMASK surface. */
if (config->info.fmask_surf_index &&
/* This counter starts from 1 instead of 0. */
xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
xin.flags = in->flags;
- xin.swizzleMode = in->swizzleMode;
+ xin.swizzleMode = fin.swizzleMode;
xin.resourceType = in->resourceType;
xin.format = in->format;
xin.numSamples = in->numSamples;
return ret;
assert(xout.pipeBankXor <=
- u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
- surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
+ u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
+ surf->fmask_tile_swizzle = xout.pipeBankXor;
}
}
cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
- if (in->numSamples) {
+ if (in->numSamples > 1) {
/* FMASK is always aligned. */
cin.cMaskFlags.pipeAligned = 1;
cin.cMaskFlags.rbAligned = 1;
surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
- surf->u.gfx9.cmask_size = cout.cmaskBytes;
- surf->u.gfx9.cmask_alignment = cout.baseAlign;
+ surf->cmask_size = cout.cmaskBytes;
+ surf->cmask_alignment = cout.baseAlign;
}
}
ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
int r;
- assert(!(surf->flags & RADEON_SURF_FMASK));
-
AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
compressed = surf->blk_w == 4 && surf->blk_h == 4;
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
AddrSurfInfoIn.format = ADDR_FMT_32_32;
break;
+ case 12:
+ assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
+ break;
case 16:
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
AddrSurfInfoIn.flags.opt4space = 1;
AddrSurfInfoIn.numMipLevels = config->info.levels;
- AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
+ AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
+ if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
+ AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
+
/* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
* as 2D to avoid having shader variants for 1D vs 2D, so all shaders
* must sample 1D textures as 2D. */
}
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
- false, surf->flags,
- &AddrSurfInfoIn.swizzleMode);
+ false, &AddrSurfInfoIn.swizzleMode);
if (r)
return r;
break;
surf->num_dcc_levels = 0;
surf->surf_size = 0;
+ surf->fmask_size = 0;
surf->dcc_size = 0;
surf->htile_size = 0;
surf->htile_slice_size = 0;
surf->u.gfx9.surf_offset = 0;
surf->u.gfx9.stencil_offset = 0;
- surf->u.gfx9.fmask_size = 0;
- surf->u.gfx9.cmask_size = 0;
+ surf->cmask_size = 0;
/* Calculate texture layout information. */
r = gfx9_compute_miptree(addrlib, config, surf, compressed,
if (!AddrSurfInfoIn.flags.depth) {
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
- false, surf->flags,
- &AddrSurfInfoIn.swizzleMode);
+ false, &AddrSurfInfoIn.swizzleMode);
if (r)
return r;
} else
/* Query whether the surface is displayable. */
bool displayable = false;
- r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
+ if (!config->is_3d && !config->is_cube) {
+ r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
surf->bpe * 8, &displayable);
- if (r)
- return r;
+ if (r)
+ return r;
+ }
surf->is_displayable = displayable;
switch (surf->u.gfx9.surf.swizzle_mode) {
case ADDR_SW_4KB_R_X:
case ADDR_SW_64KB_R_X:
case ADDR_SW_VAR_R_X:
- surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
- break;
+ /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
+ * used at the same time. This case is not currently expected to occur
+ * because we don't use rotated. Enforce this restriction on all chips
+ * to facilitate testing.
+ */
+ assert(!"rotate micro tile mode is unsupported");
+ return ADDR_ERROR;
/* Z = depth. */
case ADDR_SW_4KB_Z:
assert(0);
}
- /* Temporary workaround to prevent VM faults and hangs. */
- if (info->family == CHIP_VEGA12)
- surf->u.gfx9.fmask_size *= 8;
-
return 0;
}
{
int r;
- r = surf_config_sanity(config);
+ r = surf_config_sanity(config, surf->flags);
if (r)
return r;
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