#include "amdgpu_id.h"
#include "ac_gpu_info.h"
#include "util/macros.h"
+#include "util/u_atomic.h"
#include "util/u_math.h"
#include <errno.h>
}
/**
+ * This must be called after the first level is computed.
+ *
* Copy surface-global settings like pipe/bank config from level 0 surface
- * computation.
+ * computation, and compute tile swizzle.
*/
-static void gfx6_surface_settings(const struct radeon_info* info,
- ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
- struct radeon_surf *surf)
+static int gfx6_surface_settings(ADDR_HANDLE addrlib,
+ const struct radeon_info *info,
+ const struct ac_surf_config *config,
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
+ struct radeon_surf *surf)
{
surf->surf_alignment = csio->baseAlign;
surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
} else {
surf->u.legacy.macro_tile_index = 0;
}
+
+ /* Compute tile swizzle. */
+ /* TODO: fix tile swizzle with mipmapping for SI */
+ if ((info->chip_class >= CIK || config->info.levels == 1) &&
+ config->info.surf_index &&
+ surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
+ !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
+ (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
+ ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
+ ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
+
+ AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
+ AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
+
+ AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
+ AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
+ AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
+ AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
+ AddrBaseSwizzleIn.tileMode = csio->tileMode;
+
+ int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
+ &AddrBaseSwizzleOut);
+ if (r != ADDR_OK)
+ return r;
+
+ assert(AddrBaseSwizzleOut.tileSwizzle <=
+ u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
+ surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
+ }
+ return 0;
}
/**
}
}
+ surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
surf->num_dcc_levels = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
if (level > 0)
continue;
- gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
+ r = gfx6_surface_settings(addrlib, info, config,
+ &AddrSurfInfoOut, surf);
+ if (r)
+ return r;
}
}
}
if (level == 0) {
- if (only_stencil)
- gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
+ if (only_stencil) {
+ r = gfx6_surface_settings(addrlib, info, config,
+ &AddrSurfInfoOut, surf);
+ if (r)
+ return r;
+ }
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
* complicated.
*/
if (surf->dcc_size && config->info.levels > 1) {
+ /* The smallest miplevels that are never compressed by DCC
+ * still read the DCC buffer via TC if the base level uses DCC,
+ * and for some reason the DCC buffer needs to be larger if
+ * the miptree uses non-zero tile_swizzle. Otherwise there are
+ * VM faults.
+ *
+ * "dcc_alignment * 4" was determined by trial and error.
+ */
surf->dcc_size = align64(surf->surf_size >> 8,
- info->pipe_interleave_bytes *
- info->num_tile_pipes);
+ surf->dcc_alignment * 4);
}
/* Make sure HTILE covers the whole miptree, because the shader reads
surf->htile_size *= 2;
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
-
- /* workout base swizzle */
- if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
- ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
- ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
-
- AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
- AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
- AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
- AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
- AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
- AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut);
- surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
- }
return 0;
}
surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
surf->dcc_size = dout.dccRamSize;
surf->dcc_alignment = dout.dccRamBaseAlign;
+ surf->num_dcc_levels = in->numMipLevels;
+
+ /* Disable DCC for the smallest levels. It seems to be
+ * required for DCC readability between CB and shaders
+ * when TC L2 isn't flushed. This was guessed.
+ *
+ * Alternative solutions that also work but are worse:
+ * - Disable DCC.
+ * - Flush TC L2 after rendering.
+ */
+ for (unsigned i = 1; i < in->numMipLevels; i++) {
+ if (mip_info[i].pitch *
+ mip_info[i].height * surf->bpe < 1024) {
+ surf->num_dcc_levels = i;
+ break;
+ }
+ }
}
/* FMASK */
case RADEON_SURF_MODE_1D:
case RADEON_SURF_MODE_2D:
+ if (surf->flags & RADEON_SURF_IMPORTED) {
+ AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
+ break;
+ }
+
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
&AddrSurfInfoIn.swizzleMode);
if (r)
}
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
+ surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
+ surf->num_dcc_levels = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
surf->htile_size = 0;
}
surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
- surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
switch (surf->u.gfx9.surf.swizzle_mode) {
/* S = standard. */
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