#include "ac_surface.h"
#include "amd_family.h"
-#include "addrlib/amdgpu_asic_addr.h"
+#include "addrlib/src/amdgpu_asic_addr.h"
#include "ac_gpu_info.h"
#include "util/macros.h"
#include "util/u_atomic.h"
#include <amdgpu.h>
#include <amdgpu_drm.h>
-#include "addrlib/addrinterface.h"
+#include "addrlib/inc/addrinterface.h"
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
break;
+ case CHIP_VEGA20:
+ *addrlib_family = FAMILY_AI;
+ *addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
+ break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
break;
+ case CHIP_RAVEN2:
+ *addrlib_family = FAMILY_RV;
+ *addrlib_revid = get_first(AMDGPU_RAVEN2_RANGE);
+ break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
}
}
if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
- switch (config->info.color_samples) {
+ switch (config->info.storage_samples) {
case 0:
case 1:
case 2:
return 0;
}
+void ac_compute_cmask(const struct radeon_info *info,
+ const struct ac_surf_config *config,
+ struct radeon_surf *surf)
+{
+ unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
+ unsigned num_pipes = info->num_tile_pipes;
+ unsigned cl_width, cl_height;
+
+ if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
+ return;
+
+ assert(info->chip_class <= VI);
+
+ switch (num_pipes) {
+ case 2:
+ cl_width = 32;
+ cl_height = 16;
+ break;
+ case 4:
+ cl_width = 32;
+ cl_height = 32;
+ break;
+ case 8:
+ cl_width = 64;
+ cl_height = 32;
+ break;
+ case 16: /* Hawaii */
+ cl_width = 64;
+ cl_height = 64;
+ break;
+ default:
+ assert(0);
+ return;
+ }
+
+ unsigned base_align = num_pipes * pipe_interleave_bytes;
+
+ unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
+ unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
+ unsigned slice_elements = (width * height) / (8*8);
+
+ /* Each element of CMASK is a nibble. */
+ unsigned slice_bytes = slice_elements / 2;
+
+ surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
+ if (surf->u.legacy.cmask_slice_tile_max)
+ surf->u.legacy.cmask_slice_tile_max -= 1;
+
+ unsigned num_layers;
+ if (config->is_3d)
+ num_layers = config->info.depth;
+ else if (config->is_cube)
+ num_layers = 6;
+ else
+ num_layers = config->info.array_size;
+
+ surf->cmask_alignment = MAX2(256, base_align);
+ surf->cmask_size = align(slice_bytes, base_align) * num_layers;
+}
+
/**
* Fill in the tiling information in \p surf based on the given surface config.
*
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
- MAX2(1, config->info.color_samples);
+ MAX2(1, config->info.storage_samples);
}
/* Set the micro tile type. */
return ADDR_ERROR;
}
+ ac_compute_cmask(info, config, surf);
return 0;
}
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
- bool is_fmask, unsigned flags,
- AddrSwizzleMode *swizzle_mode)
+ bool is_fmask, AddrSwizzleMode *swizzle_mode)
{
ADDR_E_RETURNCODE ret;
ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
sin.numSamples = in->numSamples;
sin.numFrags = in->numFrags;
- if (flags & RADEON_SURF_SCANOUT) {
- sin.preferredSwSet.sw_D = 1;
- /* Raven only allows S for displayable surfaces with < 64 bpp, so
- * allow it as fallback */
- sin.preferredSwSet.sw_S = 1;
- } else if (in->flags.depth || in->flags.stencil || is_fmask)
- sin.preferredSwSet.sw_Z = 1;
- else
- sin.preferredSwSet.sw_S = 1;
-
if (is_fmask) {
sin.flags.display = 0;
sin.flags.color = 0;
fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
- true, surf->flags,
- &fin.swizzleMode);
+ true, &fin.swizzleMode);
if (ret != ADDR_OK)
return ret;
/* This counter starts from 1 instead of 0. */
xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
xin.flags = in->flags;
- xin.swizzleMode = in->swizzleMode;
+ xin.swizzleMode = fin.swizzleMode;
xin.resourceType = in->resourceType;
xin.format = in->format;
xin.numSamples = in->numSamples;
surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
- surf->u.gfx9.cmask_size = cout.cmaskBytes;
- surf->u.gfx9.cmask_alignment = cout.baseAlign;
+ surf->cmask_size = cout.cmaskBytes;
+ surf->cmask_alignment = cout.baseAlign;
}
}
AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
- AddrSurfInfoIn.numFrags = MAX2(1, config->info.color_samples);
+ AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
/* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
* as 2D to avoid having shader variants for 1D vs 2D, so all shaders
}
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
- false, surf->flags,
- &AddrSurfInfoIn.swizzleMode);
+ false, &AddrSurfInfoIn.swizzleMode);
if (r)
return r;
break;
surf->htile_slice_size = 0;
surf->u.gfx9.surf_offset = 0;
surf->u.gfx9.stencil_offset = 0;
- surf->u.gfx9.cmask_size = 0;
+ surf->cmask_size = 0;
/* Calculate texture layout information. */
r = gfx9_compute_miptree(addrlib, config, surf, compressed,
if (!AddrSurfInfoIn.flags.depth) {
r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
- false, surf->flags,
- &AddrSurfInfoIn.swizzleMode);
+ false, &AddrSurfInfoIn.swizzleMode);
if (r)
return r;
} else
assert(0);
}
- /* Temporary workaround to prevent VM faults and hangs. */
- if (info->family == CHIP_VEGA12)
- surf->fmask_size *= 8;
-
return 0;
}
projects / mesa.git / blobdiff