radeonsi: use storage_samples instead of color_samples in most places

[mesa.git] / src / amd / common / ac_surface.h

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index d0249684ad2bfdfc8b718bd6f0147e5adf9f5030..8ba964e64ec2543ebd05c2fd68a7bba4c4a0ba68 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -80,9 +80,6 @@ struct legacy_surf_level {
 };
 
 struct legacy_surf_fmask {
-    uint64_t size;
-    unsigned alignment;
-    unsigned tile_swizzle;
     unsigned slice_tile_max; /* max 4M */
     uint8_t tiling_index;    /* max 31 */
     uint8_t bankh;           /* max 8 */
@@ -112,6 +109,7 @@ struct legacy_surf_layout {
     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
     struct legacy_surf_fmask    fmask;
+    unsigned                    cmask_slice_tile_max;
 };
 
 /* Same as addrlib - AddrResourceType. */
@@ -153,13 +151,6 @@ struct gfx9_surf_layout {
     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 
     uint64_t                    stencil_offset; /* separate stencil */
-    uint64_t                    fmask_size;
-    uint64_t                    cmask_size;
-
-    uint32_t                    fmask_alignment;
-    uint32_t                    cmask_alignment;
-
-    uint8_t                     fmask_tile_swizzle;
 };
 
 struct radeon_surf {
@@ -199,18 +190,24 @@ struct radeon_surf {
      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
      */
     uint8_t                     tile_swizzle;
+    uint8_t                     fmask_tile_swizzle;
 
     uint64_t                    surf_size;
+    uint64_t                    fmask_size;
+    uint32_t                    surf_alignment;
+    uint32_t                    fmask_alignment;
+
     /* DCC and HTILE are very small. */
     uint32_t                    dcc_size;
-    uint32_t                    htile_size;
+    uint32_t                    dcc_alignment;
 
+    uint32_t                    htile_size;
     uint32_t                    htile_slice_size;
-
-    uint32_t                    surf_alignment;
-    uint32_t                    dcc_alignment;
     uint32_t                    htile_alignment;
 
+    uint32_t                    cmask_size;
+    uint32_t                    cmask_alignment;
+
     union {
         /* R600-VI return values.
          *
@@ -228,7 +225,8 @@ struct ac_surf_info {
        uint32_t width;
        uint32_t height;
        uint32_t depth;
-       uint8_t samples;
+       uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
+       uint8_t storage_samples; /* For color: allocated samples */
        uint8_t levels;
        uint8_t num_channels; /* heuristic for displayability */
        uint16_t array_size;
@@ -251,6 +249,10 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
                       enum radeon_surf_mode mode,
                       struct radeon_surf *surf);
 
+void ac_compute_cmask(const struct radeon_info *info,
+                     const struct ac_surf_config *config,
+                     struct radeon_surf *surf);
+
 #ifdef __cplusplus
 }
 #endif