ac: add more fields to ac_gpu_info

[mesa.git] / src / amd / common / ac_surface.h

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 0c8a7b11380ba35ea07a7f789ea43dab4ca2fff1..a552383caf02f906b1b4092e5babeef384052dfc 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -71,6 +71,9 @@ enum radeon_micro_mode {
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
 #define RADEON_SURF_FORCE_SWIZZLE_MODE          (1 << 28)
+#define RADEON_SURF_NO_FMASK                    (1 << 29)
+#define RADEON_SURF_NO_HTILE                    (1 << 30)
+#define RADEON_SURF_FORCE_MICRO_TILE_MODE       (1u << 31)
 
 struct legacy_surf_level {
     uint64_t                    offset;
@@ -152,6 +155,8 @@ struct gfx9_surf_layout {
     uint64_t                    surf_slice_size;
     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
+    /* Mipmap level pitch in elements. Only valid for LINEAR. */
+    uint16_t                    pitch[RADEON_SURF_MAX_LEVELS];
 
     uint64_t                    stencil_offset; /* separate stencil */
 
@@ -225,6 +230,15 @@ struct radeon_surf {
     uint32_t                    cmask_slice_size;
     uint32_t                    cmask_alignment;
 
+    /* All buffers combined. */
+    uint64_t                    htile_offset;
+    uint64_t                    fmask_offset;
+    uint64_t                    cmask_offset;
+    uint64_t                    dcc_offset;
+    uint64_t                    display_dcc_offset;
+    uint64_t                    dcc_retile_map_offset;
+    uint64_t                    total_size;
+
     union {
         /* Return values for GFX8 and older.
          *
@@ -253,6 +267,7 @@ struct ac_surf_info {
 
 struct ac_surf_config {
        struct ac_surf_info info;
+       unsigned is_1d : 1;
        unsigned is_3d : 1;
        unsigned is_cube : 1;
 };