meson: build r600 driver

[mesa.git] / src / amd / common / ac_surface.h

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 3eaef639aad61e06b7f36dfca5e69e71a6841c2c..f18548f73e46e245dea38315eb95952379a146dc 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -62,21 +62,21 @@ enum radeon_micro_mode {
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
-#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
+#define RADEON_SURF_SHAREABLE                   (1 << 26)
 
 struct legacy_surf_level {
     uint64_t                    offset;
-    uint64_t                    slice_size;
-    uint64_t                    dcc_offset;
-    uint64_t                    dcc_fast_clear_size;
-    uint16_t                    nblk_x;
-    uint16_t                    nblk_y;
-    enum radeon_surf_mode       mode;
+    uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
+    uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
+    uint32_t                    dcc_fast_clear_size;
+    unsigned                    nblk_x:15;
+    unsigned                    nblk_y:15;
+    enum radeon_surf_mode       mode:2;
 };
 
 struct legacy_surf_layout {
@@ -97,7 +97,6 @@ struct legacy_surf_layout {
     unsigned                    depth_adjusted:1;
     unsigned                    stencil_adjusted:1;
 
-    uint8_t                     tile_swizzle;
     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
@@ -131,11 +130,12 @@ struct gfx9_surf_layout {
     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
+    uint16_t                    surf_pitch; /* in blocks */
+    uint16_t                    surf_height;
+
     uint64_t                    surf_offset; /* 0 unless imported with an offset */
     /* The size of the 2D plane containing all mipmap levels. */
     uint64_t                    surf_slice_size;
-    uint16_t                    surf_pitch; /* in blocks */
-    uint16_t                    surf_height;
     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 
@@ -160,6 +160,9 @@ struct radeon_surf {
      */
     unsigned                    num_dcc_levels:4;
     unsigned                    is_linear:1;
+    unsigned                    has_stencil:1;
+    /* This might be true even if micro_tile_mode isn't displayable or rotated. */
+    unsigned                    is_displayable:1;
     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
     unsigned                    micro_tile_mode:3;
     uint32_t                    flags;
@@ -168,9 +171,25 @@ struct radeon_surf {
      * they will be treated as hints (e.g. bankw, bankh) and might be
      * changed by the calculator.
      */
+
+    /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
+     * The value is the same for all mipmap levels. Supported tile modes:
+     * - GFX6: Only macro tiling.
+     * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
+     *
+     * Only these surfaces are allowed to set it:
+     * - color (if it doesn't have to be displayable)
+     * - DCC (same tile swizzle as color)
+     * - FMASK
+     * - CMASK if it's TC-compatible or if the gen is GFX9
+     * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
+     */
+    uint8_t                     tile_swizzle;
+
     uint64_t                    surf_size;
-    uint64_t                    dcc_size;
-    uint64_t                    htile_size;
+    /* DCC and HTILE are very small. */
+    uint32_t                    dcc_size;
+    uint32_t                    htile_size;
 
     uint32_t                    htile_slice_size;
 
@@ -195,10 +214,10 @@ struct ac_surf_info {
        uint32_t width;
        uint32_t height;
        uint32_t depth;
-       uint32_t surf_index;
        uint8_t samples;
        uint8_t levels;
        uint16_t array_size;
+       uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 };
 
 struct ac_surf_config {