namespace aco {
-struct output_state {
- uint8_t mask[VARYING_SLOT_VAR31 + 1];
- Temp outputs[VARYING_SLOT_VAR31 + 1][4];
+struct shader_io_state {
+ uint8_t mask[VARYING_SLOT_MAX];
+ Temp temps[VARYING_SLOT_MAX * 4u];
+
+ shader_io_state() {
+ memset(mask, 0, sizeof(mask));
+ std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1));
+ }
};
struct isel_context {
nir_shader *shader;
uint32_t constant_data_offset;
Block *block;
- bool *divergent_vals;
std::unique_ptr<Temp[]> allocated;
std::unordered_map<unsigned, std::array<Temp,NIR_MAX_VEC_COMPONENTS>> allocated_vec;
Stage stage; /* Stage */
/* GS inputs */
Temp gs_wave_id;
- /* gathered information */
- uint64_t input_masks[MESA_SHADER_COMPUTE];
- uint64_t output_masks[MESA_SHADER_COMPUTE];
-
/* VS output information */
bool export_clip_dists;
unsigned num_clip_distances;
unsigned num_cull_distances;
/* tessellation information */
+ unsigned tcs_tess_lvl_out_loc;
+ unsigned tcs_tess_lvl_in_loc;
+ uint64_t tcs_temp_only_inputs;
uint32_t tcs_num_inputs;
+ uint32_t tcs_num_outputs;
+ uint32_t tcs_num_patch_outputs;
uint32_t tcs_num_patches;
+ bool tcs_in_out_eq = false;
- /* VS, FS or GS output information */
- output_state outputs;
+ /* I/O information */
+ shader_io_state inputs;
+ shader_io_state outputs;
+ uint8_t output_drv_loc_to_var_slot[MESA_SHADER_COMPUTE][VARYING_SLOT_MAX];
+ uint8_t output_tcs_patch_drv_loc_to_var_slot[VARYING_SLOT_MAX];
};
Temp get_arg(isel_context *ctx, struct ac_arg arg)
* block instead. This is so that we can use any SGPR live-out of the side
* without the branch without creating a linear phi in the invert or merge block. */
bool
-sanitize_if(nir_function_impl *impl, bool *divergent, nir_if *nif)
+sanitize_if(nir_function_impl *impl, nir_if *nif)
{
- if (!divergent[nif->condition.ssa->index])
- return false;
+ //TODO: skip this if the condition is uniform and there are no divergent breaks/continues?
nir_block *then_block = nir_if_last_then_block(nif);
nir_block *else_block = nir_if_last_else_block(nif);
}
bool
-sanitize_cf_list(nir_function_impl *impl, bool *divergent, struct exec_list *cf_list)
+sanitize_cf_list(nir_function_impl *impl, struct exec_list *cf_list)
{
bool progress = false;
foreach_list_typed(nir_cf_node, cf_node, node, cf_list) {
break;
case nir_cf_node_if: {
nir_if *nif = nir_cf_node_as_if(cf_node);
- progress |= sanitize_cf_list(impl, divergent, &nif->then_list);
- progress |= sanitize_cf_list(impl, divergent, &nif->else_list);
- progress |= sanitize_if(impl, divergent, nif);
+ progress |= sanitize_cf_list(impl, &nif->then_list);
+ progress |= sanitize_cf_list(impl, &nif->else_list);
+ progress |= sanitize_if(impl, nif);
break;
}
case nir_cf_node_loop: {
nir_loop *loop = nir_cf_node_as_loop(cf_node);
- progress |= sanitize_cf_list(impl, divergent, &loop->body);
+ progress |= sanitize_cf_list(impl, &loop->body);
break;
}
case nir_cf_node_function:
return progress;
}
+RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, unsigned bitsize)
+{
+ if (bitsize == 1)
+ return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components);
+ else
+ return RegClass::get(type, components * bitsize / 8u);
+}
+
void init_context(isel_context *ctx, nir_shader *shader)
{
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
unsigned lane_mask_size = ctx->program->lane_mask.size();
ctx->shader = shader;
- ctx->divergent_vals = nir_divergence_analysis(shader, nir_divergence_view_index_uniform);
+ nir_divergence_analysis(shader, nir_divergence_view_index_uniform);
/* sanitize control flow */
nir_metadata_require(impl, nir_metadata_dominance);
- sanitize_cf_list(impl, ctx->divergent_vals, &impl->body);
+ sanitize_cf_list(impl, &impl->body);
nir_metadata_preserve(impl, (nir_metadata)~nir_metadata_block_index);
/* we'll need this for isel */
switch(instr->type) {
case nir_instr_type_alu: {
nir_alu_instr *alu_instr = nir_instr_as_alu(instr);
- unsigned size = alu_instr->dest.dest.ssa.num_components;
- if (alu_instr->dest.dest.ssa.bit_size == 64)
- size *= 2;
RegType type = RegType::sgpr;
switch(alu_instr->op) {
case nir_op_fmul:
case nir_op_fround_even:
case nir_op_fsin:
case nir_op_fcos:
+ case nir_op_f2f16:
+ case nir_op_f2f16_rtz:
+ case nir_op_f2f16_rtne:
case nir_op_f2f32:
case nir_op_f2f64:
+ case nir_op_u2f16:
case nir_op_u2f32:
case nir_op_u2f64:
+ case nir_op_i2f16:
case nir_op_i2f32:
case nir_op_i2f64:
case nir_op_pack_half_2x16:
case nir_op_cube_face_coord:
type = RegType::vgpr;
break;
- case nir_op_flt:
- case nir_op_fge:
- case nir_op_feq:
- case nir_op_fne:
- case nir_op_ilt:
- case nir_op_ige:
- case nir_op_ult:
- case nir_op_uge:
- case nir_op_ieq:
- case nir_op_ine:
- case nir_op_i2b1:
- size = lane_mask_size;
- break;
+ case nir_op_f2i16:
+ case nir_op_f2u16:
+ case nir_op_f2i32:
+ case nir_op_f2u32:
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_b2i32:
+ case nir_op_b2b32:
+ case nir_op_b2f16:
case nir_op_b2f32:
- case nir_op_f2i32:
- case nir_op_f2u32:
- type = ctx->divergent_vals[alu_instr->dest.dest.ssa.index] ? RegType::vgpr : RegType::sgpr;
- break;
- case nir_op_bcsel:
- if (alu_instr->dest.dest.ssa.bit_size == 1) {
- size = lane_mask_size;
- } else {
- if (ctx->divergent_vals[alu_instr->dest.dest.ssa.index]) {
- type = RegType::vgpr;
- } else {
- if (allocated[alu_instr->src[1].src.ssa->index].type() == RegType::vgpr ||
- allocated[alu_instr->src[2].src.ssa->index].type() == RegType::vgpr) {
- type = RegType::vgpr;
- }
- }
- if (alu_instr->src[1].src.ssa->num_components == 1 && alu_instr->src[2].src.ssa->num_components == 1) {
- assert(allocated[alu_instr->src[1].src.ssa->index].size() == allocated[alu_instr->src[2].src.ssa->index].size());
- size = allocated[alu_instr->src[1].src.ssa->index].size();
- }
- }
- break;
case nir_op_mov:
- if (alu_instr->dest.dest.ssa.bit_size == 1) {
- size = lane_mask_size;
- } else {
- type = ctx->divergent_vals[alu_instr->dest.dest.ssa.index] ? RegType::vgpr : RegType::sgpr;
- }
+ type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
break;
+ case nir_op_bcsel:
+ type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
+ /* fallthrough */
default:
- if (alu_instr->dest.dest.ssa.bit_size == 1) {
- size = lane_mask_size;
- } else {
- for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++) {
- if (allocated[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr)
- type = RegType::vgpr;
- }
+ for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++) {
+ if (allocated[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr)
+ type = RegType::vgpr;
}
break;
}
- allocated[alu_instr->dest.dest.ssa.index] = Temp(0, RegClass(type, size));
+
+ RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components, alu_instr->dest.dest.ssa.bit_size);
+ allocated[alu_instr->dest.dest.ssa.index] = Temp(0, rc);
break;
}
case nir_instr_type_load_const: {
- unsigned size = nir_instr_as_load_const(instr)->def.num_components;
- if (nir_instr_as_load_const(instr)->def.bit_size == 64)
- size *= 2;
- else if (nir_instr_as_load_const(instr)->def.bit_size == 1)
- size *= lane_mask_size;
- allocated[nir_instr_as_load_const(instr)->def.index] = Temp(0, RegClass(RegType::sgpr, size));
+ unsigned num_components = nir_instr_as_load_const(instr)->def.num_components;
+ unsigned bit_size = nir_instr_as_load_const(instr)->def.bit_size;
+ RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
+ allocated[nir_instr_as_load_const(instr)->def.index] = Temp(0, rc);
break;
}
case nir_instr_type_intrinsic: {
nir_intrinsic_instr *intrinsic = nir_instr_as_intrinsic(instr);
if (!nir_intrinsic_infos[intrinsic->intrinsic].has_dest)
break;
- unsigned size = intrinsic->dest.ssa.num_components;
- if (intrinsic->dest.ssa.bit_size == 64)
- size *= 2;
RegType type = RegType::sgpr;
switch(intrinsic->intrinsic) {
case nir_intrinsic_load_push_constant:
case nir_intrinsic_read_first_invocation:
case nir_intrinsic_read_invocation:
case nir_intrinsic_first_invocation:
- type = RegType::sgpr;
- if (intrinsic->dest.ssa.bit_size == 1)
- size = lane_mask_size;
- break;
case nir_intrinsic_ballot:
type = RegType::sgpr;
break;
case nir_intrinsic_masked_swizzle_amd:
case nir_intrinsic_inclusive_scan:
case nir_intrinsic_exclusive_scan:
- if (intrinsic->dest.ssa.bit_size == 1) {
- size = lane_mask_size;
- type = RegType::sgpr;
- } else if (!ctx->divergent_vals[intrinsic->dest.ssa.index]) {
- type = RegType::sgpr;
- } else {
- type = RegType::vgpr;
- }
- break;
- case nir_intrinsic_load_view_index:
- type = ctx->stage == fragment_fs ? RegType::vgpr : RegType::sgpr;
- break;
- case nir_intrinsic_load_front_face:
- case nir_intrinsic_load_helper_invocation:
- case nir_intrinsic_is_helper_invocation:
- type = RegType::sgpr;
- size = lane_mask_size;
- break;
case nir_intrinsic_reduce:
- if (intrinsic->dest.ssa.bit_size == 1) {
- size = lane_mask_size;
- type = RegType::sgpr;
- } else if (!ctx->divergent_vals[intrinsic->dest.ssa.index]) {
- type = RegType::sgpr;
- } else {
- type = RegType::vgpr;
- }
- break;
case nir_intrinsic_load_ubo:
case nir_intrinsic_load_ssbo:
case nir_intrinsic_load_global:
case nir_intrinsic_vulkan_resource_index:
- type = ctx->divergent_vals[intrinsic->dest.ssa.index] ? RegType::vgpr : RegType::sgpr;
- break;
- /* due to copy propagation, the swizzled imov is removed if num dest components == 1 */
case nir_intrinsic_load_shared:
- if (ctx->divergent_vals[intrinsic->dest.ssa.index])
- type = RegType::vgpr;
- else
- type = RegType::sgpr;
+ type = nir_dest_is_divergent(intrinsic->dest) ? RegType::vgpr : RegType::sgpr;
+ break;
+ case nir_intrinsic_load_view_index:
+ type = ctx->stage == fragment_fs ? RegType::vgpr : RegType::sgpr;
break;
default:
for (unsigned i = 0; i < nir_intrinsic_infos[intrinsic->intrinsic].num_srcs; i++) {
}
break;
}
- allocated[intrinsic->dest.ssa.index] = Temp(0, RegClass(type, size));
+ RegClass rc = get_reg_class(ctx, type, intrinsic->dest.ssa.num_components, intrinsic->dest.ssa.bit_size);
+ allocated[intrinsic->dest.ssa.index] = Temp(0, rc);
switch(intrinsic->intrinsic) {
case nir_intrinsic_load_barycentric_sample:
if (tex->dest.ssa.bit_size == 64)
size *= 2;
- if (tex->op == nir_texop_texture_samples)
- assert(!ctx->divergent_vals[tex->dest.ssa.index]);
- if (ctx->divergent_vals[tex->dest.ssa.index])
+ if (tex->op == nir_texop_texture_samples) {
+ assert(!tex->dest.ssa.divergent);
+ }
+ if (nir_dest_is_divergent(tex->dest))
allocated[tex->dest.ssa.index] = Temp(0, RegClass(RegType::vgpr, size));
else
allocated[tex->dest.ssa.index] = Temp(0, RegClass(RegType::sgpr, size));
break;
}
case nir_instr_type_ssa_undef: {
- unsigned size = nir_instr_as_ssa_undef(instr)->def.num_components;
- if (nir_instr_as_ssa_undef(instr)->def.bit_size == 64)
- size *= 2;
- else if (nir_instr_as_ssa_undef(instr)->def.bit_size == 1)
- size *= lane_mask_size;
- allocated[nir_instr_as_ssa_undef(instr)->def.index] = Temp(0, RegClass(RegType::sgpr, size));
+ unsigned num_components = nir_instr_as_ssa_undef(instr)->def.num_components;
+ unsigned bit_size = nir_instr_as_ssa_undef(instr)->def.bit_size;
+ RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
+ allocated[nir_instr_as_ssa_undef(instr)->def.index] = Temp(0, rc);
break;
}
case nir_instr_type_phi: {
break;
}
- if (ctx->divergent_vals[phi->dest.ssa.index]) {
+ if (nir_dest_is_divergent(phi->dest)) {
type = RegType::vgpr;
} else {
type = RegType::sgpr;
}
}
- size *= phi->dest.ssa.bit_size == 64 ? 2 : 1;
- RegClass rc = RegClass(type, size);
+ RegClass rc = get_reg_class(ctx, type, phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
if (rc != allocated[phi->dest.ssa.index].regClass()) {
done = false;
} else {
return false;
switch (low->intrinsic) {
- case nir_intrinsic_load_ubo:
- case nir_intrinsic_load_ssbo:
+ case nir_intrinsic_load_global:
+ case nir_intrinsic_store_global:
+ return align % 4 == 0;
case nir_intrinsic_store_ssbo:
+ if (low->src[0].ssa->bit_size < 32 || high->src[0].ssa->bit_size < 32)
+ return false;
+ return align % 4 == 0;
+ case nir_intrinsic_load_ssbo:
+ if (low->dest.ssa.bit_size < 32 || high->dest.ssa.bit_size < 32)
+ return false;
+ case nir_intrinsic_load_ubo:
case nir_intrinsic_load_push_constant:
return align % 4 == 0;
case nir_intrinsic_load_deref:
if (outinfo->writes_pointsize || outinfo->writes_viewport_index || outinfo->writes_layer)
pos_written |= 1 << 1;
- uint64_t mask = ctx->output_masks[nir->info.stage];
+ uint64_t mask = nir->info.outputs_written;
while (mask) {
int idx = u_bit_scan64(&mask);
- if (idx >= VARYING_SLOT_VAR0 || idx == VARYING_SLOT_LAYER || idx == VARYING_SLOT_PRIMITIVE_ID ||
+ if (idx >= VARYING_SLOT_VAR0 || idx == VARYING_SLOT_LAYER ||
+ idx == VARYING_SLOT_PRIMITIVE_ID || idx == VARYING_SLOT_VIEWPORT ||
((idx == VARYING_SLOT_CLIP_DIST0 || idx == VARYING_SLOT_CLIP_DIST1) && export_clip_dists)) {
if (outinfo->vs_output_param_offset[idx] == AC_EXP_PARAM_UNDEFINED)
outinfo->vs_output_param_offset[idx] = outinfo->param_exports++;
}
nir_foreach_variable(variable, &nir->outputs)
{
- if (ctx->stage == vertex_geometry_gs)
- variable->data.driver_location = util_bitcount64(ctx->output_masks[nir->info.stage] & ((1ull << variable->data.location) - 1ull)) * 4;
- else if (ctx->stage == vertex_es ||
- ctx->stage == vertex_ls ||
- ctx->stage == vertex_tess_control_hs)
- // TODO: make this more compact
- variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot) variable->data.location) * 4;
- else if (ctx->stage == vertex_vs)
+ if (ctx->stage == vertex_vs || ctx->stage == ngg_vertex_gs)
variable->data.driver_location = variable->data.location * 4;
- else
- unreachable("Unsupported VS stage");
+
+ assert(variable->data.location >= 0 && variable->data.location <= UINT8_MAX);
+ ctx->output_drv_loc_to_var_slot[MESA_SHADER_VERTEX][variable->data.driver_location / 4] = variable->data.location;
}
- if (ctx->stage == vertex_vs) {
+ if (ctx->stage == vertex_vs || ctx->stage == ngg_vertex_gs) {
radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
setup_vs_output_info(ctx, nir, outinfo->export_prim_id,
ctx->options->key.vs_common_out.export_clip_dists, outinfo);
- } else if (ctx->stage == vertex_geometry_gs || ctx->stage == vertex_es) {
- /* TODO: radv_nir_shader_info_pass() already sets this but it's larger
- * than it needs to be in order to set it better, we have to improve
- * radv_nir_shader_info_pass() because gfx9_get_gs_info() uses
- * esgs_itemsize and has to be done before compilation
- */
- /* radv_es_output_info *outinfo = &ctx->program->info->vs.es_info;
- outinfo->esgs_itemsize = util_bitcount64(ctx->output_masks[nir->info.stage]) * 16u; */
+ } else if (ctx->stage == vertex_ls) {
+ ctx->tcs_num_inputs = ctx->program->info->vs.num_linked_outputs;
+ }
+
+ if (ctx->stage == ngg_vertex_gs && ctx->args->options->key.vs_common_out.export_prim_id) {
+ /* We need to store the primitive IDs in LDS */
+ unsigned lds_size = ctx->program->info->ngg_info.esgs_ring_size;
+ ctx->program->config->lds_size = (lds_size + ctx->program->lds_alloc_granule - 1) /
+ ctx->program->lds_alloc_granule;
}
}
void setup_gs_variables(isel_context *ctx, nir_shader *nir)
{
- if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
- nir_foreach_variable(variable, &nir->inputs) {
- variable->data.driver_location = util_bitcount64(ctx->input_masks[nir->info.stage] & ((1ull << variable->data.location) - 1ull)) * 4;
- }
- } else if (ctx->stage == geometry_gs) {
- //TODO: make this more compact
- nir_foreach_variable(variable, &nir->inputs) {
- variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot)variable->data.location) * 4;
- }
- } else {
- unreachable("Unsupported GS stage.");
- }
+ if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
+ ctx->program->config->lds_size = ctx->program->info->gs_ring_info.lds_size; /* Already in units of the alloc granularity */
nir_foreach_variable(variable, &nir->outputs) {
variable->data.driver_location = variable->data.location * 4;
}
void
-setup_tcs_variables(isel_context *ctx, nir_shader *nir)
+setup_tcs_info(isel_context *ctx, nir_shader *nir)
{
- switch (ctx->stage) {
- case tess_control_hs:
- ctx->tcs_num_inputs = ctx->args->options->key.tcs.num_inputs;
- break;
- case vertex_tess_control_hs:
- ctx->tcs_num_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
- break;
- default:
- unreachable("Unsupported TCS shader stage");
+ /* When the number of TCS input and output vertices are the same (typically 3):
+ * - There is an equal amount of LS and HS invocations
+ * - In case of merged LSHS shaders, the LS and HS halves of the shader
+ * always process the exact same vertex. We can use this knowledge to optimize them.
+ */
+ ctx->tcs_in_out_eq =
+ ctx->stage == vertex_tess_control_hs &&
+ ctx->args->options->key.tcs.input_vertices == nir->info.tess.tcs_vertices_out;
+
+ if (ctx->tcs_in_out_eq) {
+ ctx->tcs_temp_only_inputs = ~nir->info.tess.tcs_cross_invocation_inputs_read &
+ ~nir->info.inputs_read_indirectly &
+ nir->info.inputs_read;
}
+ ctx->tcs_num_inputs = ctx->program->info->tcs.num_linked_inputs;
+ ctx->tcs_num_outputs = ctx->program->info->tcs.num_linked_outputs;
+ ctx->tcs_num_patch_outputs = ctx->program->info->tcs.num_linked_patch_outputs;
+
ctx->tcs_num_patches = get_tcs_num_patches(
ctx->args->options->key.tcs.input_vertices,
nir->info.tess.tcs_vertices_out,
ctx->tcs_num_inputs,
- ctx->args->shader_info->tcs.outputs_written,
- ctx->args->shader_info->tcs.patch_outputs_written,
+ ctx->tcs_num_outputs,
+ ctx->tcs_num_patch_outputs,
ctx->args->options->tess_offchip_block_dw_size,
ctx->args->options->chip_class,
ctx->args->options->family);
nir->info.tess.tcs_vertices_out,
ctx->tcs_num_inputs,
ctx->tcs_num_patches,
- ctx->args->shader_info->tcs.outputs_written,
- ctx->args->shader_info->tcs.patch_outputs_written);
+ ctx->tcs_num_outputs,
+ ctx->tcs_num_patch_outputs);
ctx->args->shader_info->tcs.num_patches = ctx->tcs_num_patches;
ctx->args->shader_info->tcs.lds_size = lds_size;
ctx->program->config->lds_size = (lds_size + ctx->program->lds_alloc_granule - 1) /
ctx->program->lds_alloc_granule;
+}
- nir_foreach_variable(variable, &nir->inputs) {
- variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot) variable->data.location) * 4;
- }
-
+void
+setup_tcs_variables(isel_context *ctx, nir_shader *nir)
+{
nir_foreach_variable(variable, &nir->outputs) {
- variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot) variable->data.location) * 4;
+ assert(variable->data.location >= 0 && variable->data.location <= UINT8_MAX);
+
+ if (variable->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
+ ctx->tcs_tess_lvl_out_loc = variable->data.driver_location * 4u;
+ else if (variable->data.location == VARYING_SLOT_TESS_LEVEL_INNER)
+ ctx->tcs_tess_lvl_in_loc = variable->data.driver_location * 4u;
+
+ if (variable->data.patch)
+ ctx->output_tcs_patch_drv_loc_to_var_slot[variable->data.driver_location / 4] = variable->data.location;
+ else
+ ctx->output_drv_loc_to_var_slot[MESA_SHADER_TESS_CTRL][variable->data.driver_location / 4] = variable->data.location;
}
}
setup_tes_variables(isel_context *ctx, nir_shader *nir)
{
ctx->tcs_num_patches = ctx->args->options->key.tes.num_patches;
-
- nir_foreach_variable(variable, &nir->inputs) {
- variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot) variable->data.location) * 4;
- }
+ ctx->tcs_num_outputs = ctx->program->info->tes.num_linked_inputs;
nir_foreach_variable(variable, &nir->outputs) {
- if (ctx->stage == tess_eval_vs)
+ if (ctx->stage == tess_eval_vs || ctx->stage == ngg_tess_eval_gs)
variable->data.driver_location = variable->data.location * 4;
- else if (ctx->stage == tess_eval_es)
- variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot) variable->data.location) * 4;
- else if (ctx->stage == tess_eval_geometry_gs)
- variable->data.driver_location = util_bitcount64(ctx->output_masks[nir->info.stage] & ((1ull << variable->data.location) - 1ull)) * 4;
- else
- unreachable("Unsupported TES shader stage");
}
- if (ctx->stage == tess_eval_vs) {
+ if (ctx->stage == tess_eval_vs || ctx->stage == ngg_tess_eval_gs) {
radv_vs_output_info *outinfo = &ctx->program->info->tes.outinfo;
setup_vs_output_info(ctx, nir, outinfo->export_prim_id,
ctx->options->key.vs_common_out.export_clip_dists, outinfo);
}
}
-void
-get_io_masks(isel_context *ctx, unsigned shader_count, struct nir_shader *const *shaders)
+unsigned
+lower_bit_size_callback(const nir_alu_instr *alu, void *_)
{
- for (unsigned i = 0; i < shader_count; i++) {
- nir_shader *nir = shaders[i];
- if (nir->info.stage == MESA_SHADER_COMPUTE)
- continue;
+ if (nir_op_is_vec(alu->op))
+ return 0;
- uint64_t output_mask = 0;
- nir_foreach_variable(variable, &nir->outputs) {
- const glsl_type *type = variable->type;
- if (nir_is_per_vertex_io(variable, nir->info.stage))
- type = type->fields.array;
- unsigned slots = type->count_attribute_slots(false);
- if (variable->data.compact) {
- unsigned component_count = variable->data.location_frac + type->length;
- slots = (component_count + 3) / 4;
- }
- output_mask |= ((1ull << slots) - 1) << variable->data.location;
- }
+ unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ if (nir_alu_instr_is_comparison(alu))
+ bit_size = nir_src_bit_size(alu->src[0].src);
- uint64_t input_mask = 0;
- nir_foreach_variable(variable, &nir->inputs) {
- const glsl_type *type = variable->type;
- if (nir_is_per_vertex_io(variable, nir->info.stage))
- type = type->fields.array;
- unsigned slots = type->count_attribute_slots(false);
- if (variable->data.compact) {
- unsigned component_count = variable->data.location_frac + type->length;
- slots = (component_count + 3) / 4;
- }
- input_mask |= ((1ull << slots) - 1) << variable->data.location;
- }
+ if (bit_size >= 32 || bit_size == 1)
+ return 0;
- ctx->output_masks[nir->info.stage] |= output_mask;
- if (i + 1 < shader_count)
- ctx->input_masks[shaders[i + 1]->info.stage] |= output_mask;
+ if (alu->op == nir_op_bcsel)
+ return 0;
- ctx->input_masks[nir->info.stage] |= input_mask;
- if (i)
- ctx->output_masks[shaders[i - 1]->info.stage] |= input_mask;
- }
+ const nir_op_info *info = &nir_op_infos[alu->op];
+
+ if (info->is_conversion)
+ return 0;
+
+ bool is_integer = info->output_type & (nir_type_uint | nir_type_int);
+ for (unsigned i = 0; is_integer && (i < info->num_inputs); i++)
+ is_integer = info->input_types[i] & (nir_type_uint | nir_type_int);
+
+ return is_integer ? 32 : 0;
}
void
setup_variables(ctx, nir);
/* optimize and lower memory operations */
+ if (nir_lower_explicit_io(nir, nir_var_mem_global, nir_address_format_64bit_global)) {
+ nir_opt_constant_folding(nir);
+ nir_opt_cse(nir);
+ }
+
bool lower_to_scalar = false;
bool lower_pack = false;
+ nir_variable_mode robust_modes = (nir_variable_mode)0;
+
+ if (ctx->options->robust_buffer_access) {
+ robust_modes = (nir_variable_mode)(nir_var_mem_ubo |
+ nir_var_mem_ssbo |
+ nir_var_mem_global |
+ nir_var_mem_push_const);
+ }
+
if (nir_opt_load_store_vectorize(nir,
(nir_variable_mode)(nir_var_mem_ssbo | nir_var_mem_ubo |
- nir_var_mem_push_const | nir_var_mem_shared),
- mem_vectorize_callback)) {
+ nir_var_mem_push_const | nir_var_mem_shared |
+ nir_var_mem_global),
+ mem_vectorize_callback, robust_modes)) {
lower_to_scalar = true;
lower_pack = true;
}
if (nir->info.stage != MESA_SHADER_COMPUTE)
nir_lower_io(nir, (nir_variable_mode)(nir_var_shader_in | nir_var_shader_out), type_size, (nir_lower_io_options)0);
- nir_lower_explicit_io(nir, nir_var_mem_global, nir_address_format_64bit_global);
if (lower_to_scalar)
nir_lower_alu_to_scalar(nir, NULL, NULL);
// TODO: implement logic64 in aco, it's more effective for sgprs
nir_lower_int64(nir, nir->options->lower_int64_options);
+ if (nir_lower_bit_size(nir, lower_bit_size_callback, NULL))
+ nir_copy_prop(nir); /* allow nir_opt_idiv_const() to optimize lowered divisions */
+
nir_opt_idiv_const(nir, 32);
nir_lower_idiv(nir, nir_lower_idiv_precise);
nir_index_ssa_defs(func);
}
+void
+setup_xnack(Program *program)
+{
+ switch (program->family) {
+ /* GFX8 APUs */
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ /* GFX9 APUS */
+ case CHIP_RAVEN:
+ case CHIP_RAVEN2:
+ case CHIP_RENOIR:
+ program->xnack_enabled = true;
+ break;
+ default:
+ break;
+ }
+}
+
isel_context
setup_isel_context(Program* program,
unsigned shader_count,
}
bool gfx9_plus = args->options->chip_class >= GFX9;
bool ngg = args->shader_info->is_ngg && args->options->chip_class >= GFX10;
- if (program->stage == sw_vs && args->shader_info->vs.as_es)
+ if (program->stage == sw_vs && args->shader_info->vs.as_es && !ngg)
program->stage |= hw_es;
- else if (program->stage == sw_vs && !args->shader_info->vs.as_ls)
+ else if (program->stage == sw_vs && !args->shader_info->vs.as_ls && !ngg)
program->stage |= hw_vs;
+ else if (program->stage == sw_vs && ngg)
+ program->stage |= hw_ngg_gs; /* GFX10/NGG: VS without GS uses the HW GS stage */
else if (program->stage == sw_gs)
program->stage |= hw_gs;
else if (program->stage == sw_fs)
program->stage |= hw_hs; /* GFX9-10: VS+TCS merged into a Hull Shader */
else if (program->stage == sw_tes && !args->shader_info->tes.as_es && !ngg)
program->stage |= hw_vs; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
+ else if (program->stage == sw_tes && !args->shader_info->tes.as_es && ngg)
+ program->stage |= hw_ngg_gs; /* GFX10/NGG: TES without GS uses the HW GS stage */
else if (program->stage == sw_tes && args->shader_info->tes.as_es && !ngg)
program->stage |= hw_es; /* GFX6-8: TES is an Export Shader */
else if (program->stage == (sw_tes | sw_gs) && gfx9_plus && !ngg)
program->sgpr_limit = 104;
}
- calc_min_waves(program);
- program->vgpr_limit = get_addr_vgpr_from_waves(program, program->min_waves);
- program->sgpr_limit = get_addr_sgpr_from_waves(program, program->min_waves);
-
isel_context ctx = {};
ctx.program = program;
ctx.args = args;
ctx.options = args->options;
ctx.stage = program->stage;
- get_io_masks(&ctx, shader_count, shaders);
+ /* TODO: Check if we need to adjust min_waves for unknown workgroup sizes. */
+ if (program->stage & (hw_vs | hw_fs)) {
+ /* PS and legacy VS have separate waves, no workgroups */
+ program->workgroup_size = program->wave_size;
+ } else if (program->stage == compute_cs) {
+ /* CS sets the workgroup size explicitly */
+ unsigned* bsize = program->info->cs.block_size;
+ program->workgroup_size = bsize[0] * bsize[1] * bsize[2];
+ } else if ((program->stage & hw_es) || program->stage == geometry_gs) {
+ /* Unmerged ESGS operate in workgroups if on-chip GS (LDS rings) are enabled on GFX7-8 (not implemented in Mesa) */
+ program->workgroup_size = program->wave_size;
+ } else if (program->stage & hw_gs) {
+ /* If on-chip GS (LDS rings) are enabled on GFX9 or later, merged GS operates in workgroups */
+ assert(program->chip_class >= GFX9);
+ uint32_t es_verts_per_subgrp = G_028A44_ES_VERTS_PER_SUBGRP(program->info->gs_ring_info.vgt_gs_onchip_cntl);
+ uint32_t gs_instr_prims_in_subgrp = G_028A44_GS_INST_PRIMS_IN_SUBGRP(program->info->gs_ring_info.vgt_gs_onchip_cntl);
+ uint32_t workgroup_size = MAX2(es_verts_per_subgrp, gs_instr_prims_in_subgrp);
+ program->workgroup_size = MAX2(MIN2(workgroup_size, 256), 1);
+ } else if (program->stage == vertex_ls) {
+ /* Unmerged LS operates in workgroups */
+ program->workgroup_size = UINT_MAX; /* TODO: probably tcs_num_patches * tcs_vertices_in, but those are not plumbed to ACO for LS */
+ } else if (program->stage == tess_control_hs) {
+ /* Unmerged HS operates in workgroups, size is determined by the output vertices */
+ setup_tcs_info(&ctx, shaders[0]);
+ program->workgroup_size = ctx.tcs_num_patches * shaders[0]->info.tess.tcs_vertices_out;
+ } else if (program->stage == vertex_tess_control_hs) {
+ /* Merged LSHS operates in workgroups, but can still have a different number of LS and HS invocations */
+ setup_tcs_info(&ctx, shaders[1]);
+ program->workgroup_size = ctx.tcs_num_patches * MAX2(shaders[1]->info.tess.tcs_vertices_out, ctx.args->options->key.tcs.input_vertices);
+ } else if (program->stage & hw_ngg_gs) {
+ /* TODO: Calculate workgroup size of NGG shaders. */
+ program->workgroup_size = UINT_MAX;
+ } else {
+ unreachable("Unsupported shader stage.");
+ }
+
+ calc_min_waves(program);
+ program->vgpr_limit = get_addr_vgpr_from_waves(program, program->min_waves);
+ program->sgpr_limit = get_addr_sgpr_from_waves(program, program->min_waves);
unsigned scratch_size = 0;
if (program->stage == gs_copy_vs) {
ctx.block->loop_nest_depth = 0;
ctx.block->kind = block_kind_top_level;
+ setup_xnack(program);
+ program->sram_ecc_enabled = args->options->family == CHIP_ARCTURUS;
+ /* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */
+ program->has_fast_fma32 = program->chip_class >= GFX9;
+ if (args->options->family == CHIP_TAHITI || args->options->family == CHIP_CARRIZO || args->options->family == CHIP_HAWAII)
+ program->has_fast_fma32 = true;
+
return ctx;
}
projects / mesa.git / blobdiff