aco: do not set valid_mask for POS0 exports on GFX 10.3

[mesa.git] / src / amd / compiler / aco_opt_value_numbering.cpp

diff --git a/src/amd/compiler/aco_opt_value_numbering.cpp b/src/amd/compiler/aco_opt_value_numbering.cpp
index 4ab3d6d56e5540c681d872b3fe4207af3e8e5153..11aad20a0b09b808d5df31df20dbee558ab68945 100644 (file)
--- a/src/amd/compiler/aco_opt_value_numbering.cpp
+++ b/src/amd/compiler/aco_opt_value_numbering.cpp
@@ -86,6 +86,9 @@ struct InstrHash {
       if (instr->isDPP())
          return hash_murmur_32<DPP_instruction>(instr);
 
+      if (instr->isSDWA())
+         return hash_murmur_32<SDWA_instruction>(instr);
+
       switch (instr->format) {
       case Format::SMEM:
          return hash_murmur_32<SMEM_instruction>(instr);
@@ -199,9 +202,25 @@ struct InstrPred {
                 aDPP->neg[0] == bDPP->neg[0] &&
                 aDPP->neg[1] == bDPP->neg[1];
       }
+      if (a->isSDWA()) {
+         SDWA_instruction* aSDWA = static_cast<SDWA_instruction*>(a);
+         SDWA_instruction* bSDWA = static_cast<SDWA_instruction*>(b);
+         return aSDWA->sel[0] == bSDWA->sel[0] &&
+                aSDWA->sel[1] == bSDWA->sel[1] &&
+                aSDWA->dst_sel == bSDWA->dst_sel &&
+                aSDWA->abs[0] == bSDWA->abs[0] &&
+                aSDWA->abs[1] == bSDWA->abs[1] &&
+                aSDWA->neg[0] == bSDWA->neg[0] &&
+                aSDWA->neg[1] == bSDWA->neg[1] &&
+                aSDWA->dst_preserve == bSDWA->dst_preserve &&
+                aSDWA->clamp == bSDWA->clamp &&
+                aSDWA->omod == bSDWA->omod;
+      }
 
       switch (a->format) {
          case Format::SOPK: {
+            if (a->opcode == aco_opcode::s_getreg_b32)
+               return false;
             SOPK_instruction* aK = static_cast<SOPK_instruction*>(a);
             SOPK_instruction* bK = static_cast<SOPK_instruction*>(b);
             return aK->imm == bK->imm;
@@ -209,8 +228,12 @@ struct InstrPred {
          case Format::SMEM: {
             SMEM_instruction* aS = static_cast<SMEM_instruction*>(a);
             SMEM_instruction* bS = static_cast<SMEM_instruction*>(b);
-            return aS->can_reorder && bS->can_reorder &&
-                   aS->glc == bS->glc && aS->nv == bS->nv;
+            /* isel shouldn't be creating situations where this assertion fails */
+            assert(aS->prevent_overflow == bS->prevent_overflow);
+            return aS->sync.can_reorder() && bS->sync.can_reorder() &&
+                   aS->sync == bS->sync && aS->glc == bS->glc && aS->dlc == bS->dlc &&
+                   aS->nv == bS->nv && aS->disable_wqm == bS->disable_wqm &&
+                   aS->prevent_overflow == bS->prevent_overflow;
          }
          case Format::VINTRP: {
             Interp_instruction* aI = static_cast<Interp_instruction*>(a);
@@ -231,8 +254,8 @@ struct InstrPred {
          case Format::MTBUF: {
             MTBUF_instruction* aM = static_cast<MTBUF_instruction *>(a);
             MTBUF_instruction* bM = static_cast<MTBUF_instruction *>(b);
-            return aM->can_reorder && bM->can_reorder &&
-                   aM->barrier == bM->barrier &&
+            return aM->sync.can_reorder() && bM->sync.can_reorder() &&
+                   aM->sync == bM->sync &&
                    aM->dfmt == bM->dfmt &&
                    aM->nfmt == bM->nfmt &&
                    aM->offset == bM->offset &&
@@ -247,8 +270,8 @@ struct InstrPred {
          case Format::MUBUF: {
             MUBUF_instruction* aM = static_cast<MUBUF_instruction *>(a);
             MUBUF_instruction* bM = static_cast<MUBUF_instruction *>(b);
-            return aM->can_reorder && bM->can_reorder &&
-                   aM->barrier == bM->barrier &&
+            return aM->sync.can_reorder() && bM->sync.can_reorder() &&
+                   aM->sync == bM->sync &&
                    aM->offset == bM->offset &&
                    aM->offen == bM->offen &&
                    aM->idxen == bM->idxen &&
@@ -275,7 +298,9 @@ struct InstrPred {
                return false;
             DS_instruction* aD = static_cast<DS_instruction *>(a);
             DS_instruction* bD = static_cast<DS_instruction *>(b);
-            return aD->pass_flags == bD->pass_flags &&
+            return aD->sync.can_reorder() && bD->sync.can_reorder() &&
+                   aD->sync == bD->sync &&
+                   aD->pass_flags == bD->pass_flags &&
                    aD->gds == bD->gds &&
                    aD->offset0 == bD->offset0 &&
                    aD->offset1 == bD->offset1;
@@ -283,8 +308,8 @@ struct InstrPred {
          case Format::MIMG: {
             MIMG_instruction* aM = static_cast<MIMG_instruction*>(a);
             MIMG_instruction* bM = static_cast<MIMG_instruction*>(b);
-            return aM->can_reorder && bM->can_reorder &&
-                   aM->barrier == bM->barrier &&
+            return aM->sync.can_reorder() && bM->sync.can_reorder() &&
+                   aM->sync == bM->sync &&
                    aM->dmask == bM->dmask &&
                    aM->unrm == bM->unrm &&
                    aM->glc == bM->glc &&
@@ -384,6 +409,14 @@ void process_block(vn_ctx& ctx, Block& block)
                assert(instr->definitions[i].regClass() == orig_instr->definitions[i].regClass());
                assert(instr->definitions[i].isTemp());
                ctx.renames[instr->definitions[i].tempId()] = orig_instr->definitions[i].getTemp();
+               if (instr->definitions[i].isPrecise())
+                  orig_instr->definitions[i].setPrecise(true);
+               /* SPIR_V spec says that an instruction marked with NUW wrapping
+                * around is undefined behaviour, so we can break additions in
+                * other contexts.
+                */
+               if (instr->definitions[i].isNUW())
+                  orig_instr->definitions[i].setNUW(true);
             }
          } else {
             ctx.expr_values.erase(res.first);