namespace aco {
namespace {
+inline
+uint32_t murmur_32_scramble(uint32_t h, uint32_t k) {
+ k *= 0xcc9e2d51;
+ k = (k << 15) | (k >> 17);
+ h ^= k * 0x1b873593;
+ h = (h << 13) | (h >> 19);
+ h = h * 5 + 0xe6546b64;
+ return h;
+}
+
+template<typename T>
+uint32_t hash_murmur_32(Instruction* instr)
+{
+ uint32_t hash = uint32_t(instr->format) << 16 | uint32_t(instr->opcode);
+
+ for (const Operand& op : instr->operands)
+ hash = murmur_32_scramble(hash, op.constantValue());
+
+ /* skip format, opcode and pass_flags */
+ for (unsigned i = 2; i < (sizeof(T) >> 2); i++) {
+ uint32_t u;
+ /* Accesses it though a byte array, so doesn't violate the strict aliasing rule */
+ memcpy(&u, reinterpret_cast<uint8_t *>(instr) + i * 4, 4);
+ hash = murmur_32_scramble(hash, u);
+ }
+
+ /* Finalize. */
+ uint32_t len = instr->operands.size() + instr->definitions.size() + sizeof(T);
+ hash ^= len;
+ hash ^= hash >> 16;
+ hash *= 0x85ebca6b;
+ hash ^= hash >> 13;
+ hash *= 0xc2b2ae35;
+ hash ^= hash >> 16;
+ return hash;
+}
+
struct InstrHash {
+ /* This hash function uses the Murmur3 algorithm written by Austin Appleby
+ * https://github.com/aappleby/smhasher/blob/master/src/MurmurHash3.cpp
+ *
+ * In order to calculate the expression set, only the right-hand-side of an
+ * instruction is used for the hash, i.e. everything except the definitions.
+ */
std::size_t operator()(Instruction* instr) const
{
- uint64_t hash = (uint64_t) instr->opcode + (uint64_t) instr->format;
- for (unsigned i = 0; i < instr->operands.size(); i++) {
- Operand op = instr->operands[i];
- uint64_t val = op.isTemp() ? op.tempId() : op.isFixed() ? op.physReg() : op.constantValue();
- hash |= val << (i+1) * 8;
- }
- if (instr->isVOP3()) {
- VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(instr);
- for (unsigned i = 0; i < 3; i++) {
- hash ^= vop3->abs[i] << (i*3 + 0);
- hash ^= vop3->neg[i] << (i*3 + 2);
- }
- hash ^= vop3->opsel * 13;
- hash ^= (vop3->clamp << 28) * 13;
- hash += vop3->omod << 19;
- }
+ if (instr->isVOP3())
+ return hash_murmur_32<VOP3A_instruction>(instr);
+
+ if (instr->isDPP())
+ return hash_murmur_32<DPP_instruction>(instr);
+
+ if (instr->isSDWA())
+ return hash_murmur_32<SDWA_instruction>(instr);
+
switch (instr->format) {
case Format::SMEM:
- break;
- case Format::VINTRP: {
- Interp_instruction* interp = static_cast<Interp_instruction*>(instr);
- hash ^= interp->attribute << 13;
- hash ^= interp->component << 27;
- break;
- }
+ return hash_murmur_32<SMEM_instruction>(instr);
+ case Format::VINTRP:
+ return hash_murmur_32<Interp_instruction>(instr);
case Format::DS:
- break;
+ return hash_murmur_32<DS_instruction>(instr);
+ case Format::SOPP:
+ return hash_murmur_32<SOPP_instruction>(instr);
+ case Format::SOPK:
+ return hash_murmur_32<SOPK_instruction>(instr);
+ case Format::EXP:
+ return hash_murmur_32<Export_instruction>(instr);
+ case Format::MUBUF:
+ return hash_murmur_32<MUBUF_instruction>(instr);
+ case Format::MIMG:
+ return hash_murmur_32<MIMG_instruction>(instr);
+ case Format::MTBUF:
+ return hash_murmur_32<MTBUF_instruction>(instr);
+ case Format::FLAT:
+ return hash_murmur_32<FLAT_instruction>(instr);
+ case Format::PSEUDO_BRANCH:
+ return hash_murmur_32<Pseudo_branch_instruction>(instr);
+ case Format::PSEUDO_REDUCTION:
+ return hash_murmur_32<Pseudo_reduction_instruction>(instr);
default:
- break;
+ return hash_murmur_32<Instruction>(instr);
}
-
- return hash;
}
};
aDPP->neg[0] == bDPP->neg[0] &&
aDPP->neg[1] == bDPP->neg[1];
}
+ if (a->isSDWA()) {
+ SDWA_instruction* aSDWA = static_cast<SDWA_instruction*>(a);
+ SDWA_instruction* bSDWA = static_cast<SDWA_instruction*>(b);
+ return aSDWA->sel[0] == bSDWA->sel[0] &&
+ aSDWA->sel[1] == bSDWA->sel[1] &&
+ aSDWA->dst_sel == bSDWA->dst_sel &&
+ aSDWA->abs[0] == bSDWA->abs[0] &&
+ aSDWA->abs[1] == bSDWA->abs[1] &&
+ aSDWA->neg[0] == bSDWA->neg[0] &&
+ aSDWA->neg[1] == bSDWA->neg[1] &&
+ aSDWA->dst_preserve == bSDWA->dst_preserve &&
+ aSDWA->clamp == bSDWA->clamp &&
+ aSDWA->omod == bSDWA->omod;
+ }
switch (a->format) {
case Format::SOPK: {
+ if (a->opcode == aco_opcode::s_getreg_b32)
+ return false;
SOPK_instruction* aK = static_cast<SOPK_instruction*>(a);
SOPK_instruction* bK = static_cast<SOPK_instruction*>(b);
return aK->imm == bK->imm;
case Format::SMEM: {
SMEM_instruction* aS = static_cast<SMEM_instruction*>(a);
SMEM_instruction* bS = static_cast<SMEM_instruction*>(b);
- return aS->can_reorder && bS->can_reorder &&
- aS->glc == bS->glc && aS->nv == bS->nv;
+ /* isel shouldn't be creating situations where this assertion fails */
+ assert(aS->prevent_overflow == bS->prevent_overflow);
+ return aS->sync.can_reorder() && bS->sync.can_reorder() &&
+ aS->sync == bS->sync && aS->glc == bS->glc && aS->dlc == bS->dlc &&
+ aS->nv == bS->nv && aS->disable_wqm == bS->disable_wqm &&
+ aS->prevent_overflow == bS->prevent_overflow;
}
case Format::VINTRP: {
Interp_instruction* aI = static_cast<Interp_instruction*>(a);
aR->cluster_size == bR->cluster_size;
}
case Format::MTBUF: {
- /* this is fine since they are only used for vertex input fetches */
MTBUF_instruction* aM = static_cast<MTBUF_instruction *>(a);
MTBUF_instruction* bM = static_cast<MTBUF_instruction *>(b);
- return aM->can_reorder && bM->can_reorder &&
- aM->barrier == bM->barrier &&
+ return aM->sync.can_reorder() && bM->sync.can_reorder() &&
+ aM->sync == bM->sync &&
aM->dfmt == bM->dfmt &&
aM->nfmt == bM->nfmt &&
aM->offset == bM->offset &&
aM->offen == bM->offen &&
aM->idxen == bM->idxen &&
aM->glc == bM->glc &&
+ aM->dlc == bM->dlc &&
aM->slc == bM->slc &&
aM->tfe == bM->tfe &&
aM->disable_wqm == bM->disable_wqm;
}
+ case Format::MUBUF: {
+ MUBUF_instruction* aM = static_cast<MUBUF_instruction *>(a);
+ MUBUF_instruction* bM = static_cast<MUBUF_instruction *>(b);
+ return aM->sync.can_reorder() && bM->sync.can_reorder() &&
+ aM->sync == bM->sync &&
+ aM->offset == bM->offset &&
+ aM->offen == bM->offen &&
+ aM->idxen == bM->idxen &&
+ aM->glc == bM->glc &&
+ aM->dlc == bM->dlc &&
+ aM->slc == bM->slc &&
+ aM->tfe == bM->tfe &&
+ aM->lds == bM->lds &&
+ aM->disable_wqm == bM->disable_wqm;
+ }
/* we want to optimize these in NIR and don't hassle with load-store dependencies */
- case Format::MUBUF:
case Format::FLAT:
case Format::GLOBAL:
case Format::SCRATCH:
return false;
DS_instruction* aD = static_cast<DS_instruction *>(a);
DS_instruction* bD = static_cast<DS_instruction *>(b);
- return aD->pass_flags == bD->pass_flags &&
+ return aD->sync.can_reorder() && bD->sync.can_reorder() &&
+ aD->sync == bD->sync &&
+ aD->pass_flags == bD->pass_flags &&
aD->gds == bD->gds &&
aD->offset0 == bD->offset0 &&
aD->offset1 == bD->offset1;
case Format::MIMG: {
MIMG_instruction* aM = static_cast<MIMG_instruction*>(a);
MIMG_instruction* bM = static_cast<MIMG_instruction*>(b);
- return aM->can_reorder && bM->can_reorder &&
- aM->barrier == bM->barrier &&
+ return aM->sync.can_reorder() && bM->sync.can_reorder() &&
+ aM->sync == bM->sync &&
aM->dmask == bM->dmask &&
aM->unrm == bM->unrm &&
aM->glc == bM->glc &&
*/
uint32_t exec_id = 1;
- vn_ctx(Program* program) : program(program) {}
+ vn_ctx(Program* program) : program(program) {
+ static_assert(sizeof(Temp) == 4, "Temp must fit in 32bits");
+ unsigned size = 0;
+ for (Block& block : program->blocks)
+ size += block.instructions.size();
+ expr_values.reserve(size);
+ }
};
assert(instr->definitions[i].regClass() == orig_instr->definitions[i].regClass());
assert(instr->definitions[i].isTemp());
ctx.renames[instr->definitions[i].tempId()] = orig_instr->definitions[i].getTemp();
+ if (instr->definitions[i].isPrecise())
+ orig_instr->definitions[i].setPrecise(true);
+ /* SPIR_V spec says that an instruction marked with NUW wrapping
+ * around is undefined behaviour, so we can break additions in
+ * other contexts.
+ */
+ if (instr->definitions[i].isNUW())
+ orig_instr->definitions[i].setNUW(true);
}
} else {
ctx.expr_values.erase(res.first);
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