#include <array>
#include <map>
#include <unordered_map>
-#include <functional>
#include "aco_ir.h"
#include "sid.h"
assignment(PhysReg reg, RegClass rc) : reg(reg), rc(rc), assigned(-1) {}
};
+struct phi_info {
+ Instruction* phi;
+ unsigned block_idx;
+ std::set<Instruction*> uses;
+};
+
struct ra_ctx {
std::bitset<512> war_hint;
Program* program;
std::vector<assignment> assignments;
- std::map<unsigned, Temp> orig_names;
+ std::vector<std::unordered_map<unsigned, Temp>> renames;
+ std::vector<std::vector<Instruction*>> incomplete_phis;
+ std::vector<bool> filled;
+ std::vector<bool> sealed;
+ std::unordered_map<unsigned, Temp> orig_names;
+ std::unordered_map<unsigned, phi_info> phi_map;
+ std::unordered_map<unsigned, unsigned> affinities;
+ std::unordered_map<unsigned, Instruction*> vectors;
+ aco_ptr<Instruction> pseudo_dummy;
unsigned max_used_sgpr = 0;
unsigned max_used_vgpr = 0;
std::bitset<64> defs_done; /* see MAX_ARGS in aco_instruction_selection_setup.cpp */
- ra_ctx(Program* program) : program(program), assignments(program->peekAllocationId()) {}
+ ra_ctx(Program* program) : program(program),
+ assignments(program->peekAllocationId()),
+ renames(program->blocks.size()),
+ incomplete_phis(program->blocks.size()),
+ filled(program->blocks.size()),
+ sealed(program->blocks.size())
+ {
+ pseudo_dummy.reset(create_instruction<Instruction>(aco_opcode::p_parallelcopy, Format::PSEUDO, 0, 0));
+ }
+};
+
+bool instr_can_access_subdword(aco_ptr<Instruction>& instr)
+{
+ return instr->isSDWA() || instr->format == Format::PSEUDO;
+}
+
+struct DefInfo {
+ uint16_t lb;
+ uint16_t ub;
+ uint8_t size;
+ uint8_t stride;
+ RegClass rc;
+
+ DefInfo(ra_ctx& ctx, aco_ptr<Instruction>& instr, RegClass rc) : rc(rc) {
+ size = rc.size();
+ stride = 1;
+
+ if (rc.type() == RegType::vgpr) {
+ lb = 256;
+ ub = 256 + ctx.program->max_reg_demand.vgpr;
+ } else {
+ lb = 0;
+ ub = ctx.program->max_reg_demand.sgpr;
+ if (size == 2)
+ stride = 2;
+ else if (size >= 4)
+ stride = 4;
+ }
+
+ if (rc.is_subdword()) {
+ /* stride in bytes */
+ if(!instr_can_access_subdword(instr))
+ stride = 4;
+ else if (rc.bytes() % 4 == 0)
+ stride = 4;
+ else if (rc.bytes() % 2 == 0)
+ stride = 2;
+ }
+ }
};
class RegisterFile {
return false;
}
- void fill(PhysReg start, unsigned size, uint32_t val) {
- for (unsigned i = 0; i < size; i++)
- regs[start + i] = val;
- }
-
- void fill_subdword(PhysReg start, unsigned num_bytes, uint32_t val) {
- fill(start, DIV_ROUND_UP(num_bytes, 4), 0xF0000000);
- for (PhysReg i = start; i.reg_b < start.reg_b + num_bytes; i = PhysReg(i + 1)) {
- /* emplace or get */
- std::array<uint32_t, 4>& sub = subdword_regs.emplace(i, std::array<uint32_t, 4>{0, 0, 0, 0}).first->second;
- for (unsigned j = i.byte(); i * 4 + j < start.reg_b + num_bytes && j < 4; j++)
- sub[j] = val;
-
- if (sub == std::array<uint32_t, 4>{0, 0, 0, 0}) {
- subdword_regs.erase(i);
- regs[i] = 0;
- }
- }
- }
-
void block(PhysReg start, unsigned num_bytes) {
if (start.byte() || num_bytes % 4)
fill_subdword(start, num_bytes, 0xFFFFFFFF);
void clear(Definition def) {
clear(def.physReg(), def.regClass());
}
+
+private:
+ void fill(PhysReg start, unsigned size, uint32_t val) {
+ for (unsigned i = 0; i < size; i++)
+ regs[start + i] = val;
+ }
+
+ void fill_subdword(PhysReg start, unsigned num_bytes, uint32_t val) {
+ fill(start, DIV_ROUND_UP(num_bytes, 4), 0xF0000000);
+ for (PhysReg i = start; i.reg_b < start.reg_b + num_bytes; i = PhysReg(i + 1)) {
+ /* emplace or get */
+ std::array<uint32_t, 4>& sub = subdword_regs.emplace(i, std::array<uint32_t, 4>{0, 0, 0, 0}).first->second;
+ for (unsigned j = i.byte(); i * 4 + j < start.reg_b + num_bytes && j < 4; j++)
+ sub[j] = val;
+
+ if (sub == std::array<uint32_t, 4>{0, 0, 0, 0}) {
+ subdword_regs.erase(i);
+ regs[i] = 0;
+ }
+ }
+ }
};
}
}
-bool instr_can_access_subdword(aco_ptr<Instruction>& instr)
-{
- return instr->isSDWA() || instr->format == Format::PSEUDO;
-}
-
std::pair<PhysReg, bool> get_reg_simple(ra_ctx& ctx,
RegisterFile& reg_file,
- uint32_t lb, uint32_t ub,
- uint32_t size, uint32_t stride,
- RegClass rc)
+ DefInfo info)
{
+ uint32_t lb = info.lb;
+ uint32_t ub = info.ub;
+ uint32_t size = info.size;
+ uint32_t stride = info.stride;
+ RegClass rc = info.rc;
+
if (rc.is_subdword()) {
for (std::pair<uint32_t, std::array<uint32_t, 4>> entry : reg_file.subdword_regs) {
assert(reg_file[entry.first] == 0xF0000000);
/* best fit algorithm: find the smallest gap to fit in the variable */
if (stride == 1) {
+
+ if (rc.type() == RegType::vgpr && (size == 4 || size == 8)) {
+ info.stride = 4;
+ std::pair<PhysReg, bool> res = get_reg_simple(ctx, reg_file, info);
+ if (res.second)
+ return res;
+ }
+
unsigned best_pos = 0xFFFF;
unsigned gap_size = 0xFFFF;
unsigned next_pos = 0xFFFF;
for (std::set<std::pair<unsigned, unsigned>>::const_reverse_iterator it = vars.rbegin(); it != vars.rend(); ++it) {
unsigned id = it->second;
assignment& var = ctx.assignments[id];
- uint32_t size = var.rc.size();
- uint32_t stride = 1;
- if (var.rc.type() == RegType::sgpr) {
- if (size == 2)
- stride = 2;
- if (size > 3)
- stride = 4;
- }
+ DefInfo info = DefInfo(ctx, ctx.pseudo_dummy, var.rc);
+ uint32_t size = info.size;
/* check if this is a dead operand, then we can re-use the space from the definition */
bool is_dead_operand = false;
std::pair<PhysReg, bool> res;
if (is_dead_operand) {
if (instr->opcode == aco_opcode::p_create_vector) {
- for (unsigned i = 0, offset = 0; i < instr->operands.size(); offset += instr->operands[i].size(), i++) {
+ for (unsigned i = 0, offset = 0; i < instr->operands.size(); offset += instr->operands[i].bytes(), i++) {
if (instr->operands[i].isTemp() && instr->operands[i].tempId() == id) {
- for (unsigned j = 0; j < size; j++)
- assert(reg_file[def_reg_lo + offset + j] == 0);
- res = {PhysReg{def_reg_lo + offset}, true};
+ PhysReg reg(def_reg_lo);
+ reg.reg_b += offset;
+ assert(!reg_file.test(reg, var.rc.bytes()));
+ res = {reg, true};
break;
}
}
} else {
- res = get_reg_simple(ctx, reg_file, def_reg_lo, def_reg_hi + 1, size, stride, var.rc);
+ info.lb = def_reg_lo;
+ info.ub = def_reg_hi + 1;
+ res = get_reg_simple(ctx, reg_file, info);
}
} else {
- res = get_reg_simple(ctx, reg_file, lb, def_reg_lo, size, stride, var.rc);
+ info.lb = lb;
+ info.ub = def_reg_lo;
+ res = get_reg_simple(ctx, reg_file, info);
if (!res.second) {
- unsigned lb = (def_reg_hi + stride) & ~(stride - 1);
- res = get_reg_simple(ctx, reg_file, lb, ub, size, stride, var.rc);
+ info.lb = (def_reg_hi + info.stride) & ~(info.stride - 1);
+ info.ub = ub;
+ res = get_reg_simple(ctx, reg_file, info);
}
}
/* we use a sliding window to find potential positions */
unsigned reg_lo = lb;
unsigned reg_hi = lb + size - 1;
+ unsigned stride = var.rc.is_subdword() ? 1 : info.stride;
for (reg_lo = lb, reg_hi = lb + size - 1; reg_hi < ub; reg_lo += stride, reg_hi += stride) {
if (!is_dead_operand && ((reg_lo >= def_reg_lo && reg_lo <= def_reg_hi) ||
(reg_hi >= def_reg_lo && reg_hi <= def_reg_hi)))
std::pair<PhysReg, bool> get_reg_impl(ra_ctx& ctx,
RegisterFile& reg_file,
std::vector<std::pair<Operand, Definition>>& parallelcopies,
- uint32_t lb, uint32_t ub,
- uint32_t size, uint32_t stride,
- RegClass rc,
+ DefInfo info,
aco_ptr<Instruction>& instr)
{
+ uint32_t lb = info.lb;
+ uint32_t ub = info.ub;
+ uint32_t size = info.size;
+ uint32_t stride = info.stride;
+ RegClass rc = info.rc;
+
/* check how many free regs we have */
unsigned regs_free = reg_file.count_zero(PhysReg{lb}, ub-lb);
return {PhysReg{best_pos}, true};
}
-PhysReg get_reg(ra_ctx& ctx,
- RegisterFile& reg_file,
- RegClass rc,
- std::vector<std::pair<Operand, Definition>>& parallelcopies,
- aco_ptr<Instruction>& instr)
+bool get_reg_specified(ra_ctx& ctx,
+ RegisterFile& reg_file,
+ RegClass rc,
+ std::vector<std::pair<Operand, Definition>>& parallelcopies,
+ aco_ptr<Instruction>& instr,
+ PhysReg reg)
{
+ if (rc.is_subdword() && reg.byte() && !instr_can_access_subdword(instr))
+ return false;
+
uint32_t size = rc.size();
uint32_t stride = 1;
uint32_t lb, ub;
+
if (rc.type() == RegType::vgpr) {
lb = 256;
ub = 256 + ctx.program->max_reg_demand.vgpr;
} else {
- lb = 0;
- ub = ctx.program->max_reg_demand.sgpr;
if (size == 2)
stride = 2;
else if (size >= 4)
stride = 4;
+ if (reg % stride != 0)
+ return false;
+ lb = 0;
+ ub = ctx.program->max_reg_demand.sgpr;
}
- if (rc.is_subdword()) {
- /* stride in bytes */
- if(!instr_can_access_subdword(instr))
- stride = 4;
- else if (rc.bytes() % 4 == 0)
- stride = 4;
- else if (rc.bytes() % 2 == 0)
- stride = 2;
+ uint32_t reg_lo = reg.reg();
+ uint32_t reg_hi = reg + (size - 1);
+
+ if (reg_lo < lb || reg_hi >= ub || reg_lo > reg_hi)
+ return false;
+
+ if (reg_file.test(reg, rc.bytes()))
+ return false;
+
+ adjust_max_used_regs(ctx, rc, reg_lo);
+ return true;
+}
+
+PhysReg get_reg(ra_ctx& ctx,
+ RegisterFile& reg_file,
+ Temp temp,
+ std::vector<std::pair<Operand, Definition>>& parallelcopies,
+ aco_ptr<Instruction>& instr)
+{
+ if (ctx.affinities.find(temp.id()) != ctx.affinities.end() &&
+ ctx.assignments[ctx.affinities[temp.id()]].assigned) {
+ PhysReg reg = ctx.assignments[ctx.affinities[temp.id()]].reg;
+ if (get_reg_specified(ctx, reg_file, temp.regClass(), parallelcopies, instr, reg))
+ return reg;
}
- std::pair<PhysReg, bool> res = {{}, false};
+ if (ctx.vectors.find(temp.id()) != ctx.vectors.end()) {
+ Instruction* vec = ctx.vectors[temp.id()];
+ unsigned byte_offset = 0;
+ for (const Operand& op : vec->operands) {
+ if (op.isTemp() && op.tempId() == temp.id())
+ break;
+ else
+ byte_offset += op.bytes();
+ }
+ unsigned k = 0;
+ for (const Operand& op : vec->operands) {
+ if (op.isTemp() &&
+ op.tempId() != temp.id() &&
+ op.getTemp().type() == temp.type() &&
+ ctx.assignments[op.tempId()].assigned) {
+ PhysReg reg = ctx.assignments[op.tempId()].reg;
+ reg.reg_b += (byte_offset - k);
+ if (get_reg_specified(ctx, reg_file, temp.regClass(), parallelcopies, instr, reg))
+ return reg;
+ }
+ k += op.bytes();
+ }
+
+ DefInfo info(ctx, ctx.pseudo_dummy, vec->definitions[0].regClass());
+ std::pair<PhysReg, bool> res = get_reg_simple(ctx, reg_file, info);
+ PhysReg reg = res.first;
+ if (res.second) {
+ reg.reg_b += byte_offset;
+ /* make sure to only use byte offset if the instruction supports it */
+ if (get_reg_specified(ctx, reg_file, temp.regClass(), parallelcopies, instr, reg))
+ return reg;
+ }
+ }
+
+ DefInfo info(ctx, instr, temp.regClass());
+
/* try to find space without live-range splits */
- if (rc.type() == RegType::vgpr && (size == 4 || size == 8))
- res = get_reg_simple(ctx, reg_file, lb, ub, size, 4, rc);
- if (!res.second)
- res = get_reg_simple(ctx, reg_file, lb, ub, size, stride, rc);
+ std::pair<PhysReg, bool> res = get_reg_simple(ctx, reg_file, info);
+
if (res.second)
return res.first;
/* try to find space with live-range splits */
- res = get_reg_impl(ctx, reg_file, parallelcopies, lb, ub, size, stride, rc, instr);
+ res = get_reg_impl(ctx, reg_file, parallelcopies, info, instr);
if (res.second)
return res.first;
/* We should only fail here because keeping under the limit would require
* too many moves. */
- assert(reg_file.count_zero(PhysReg{lb}, ub-lb) >= size);
+ assert(reg_file.count_zero(PhysReg{info.lb}, info.ub-info.lb) >= info.size);
uint16_t max_addressible_sgpr = ctx.program->sgpr_limit;
uint16_t max_addressible_vgpr = ctx.program->vgpr_limit;
- if (rc.type() == RegType::vgpr && ctx.program->max_reg_demand.vgpr < max_addressible_vgpr) {
+ if (info.rc.type() == RegType::vgpr && ctx.program->max_reg_demand.vgpr < max_addressible_vgpr) {
update_vgpr_sgpr_demand(ctx.program, RegisterDemand(ctx.program->max_reg_demand.vgpr + 1, ctx.program->max_reg_demand.sgpr));
- return get_reg(ctx, reg_file, rc, parallelcopies, instr);
- } else if (rc.type() == RegType::sgpr && ctx.program->max_reg_demand.sgpr < max_addressible_sgpr) {
+ return get_reg(ctx, reg_file, temp, parallelcopies, instr);
+ } else if (info.rc.type() == RegType::sgpr && ctx.program->max_reg_demand.sgpr < max_addressible_sgpr) {
update_vgpr_sgpr_demand(ctx.program, RegisterDemand(ctx.program->max_reg_demand.vgpr, ctx.program->max_reg_demand.sgpr + 1));
- return get_reg(ctx, reg_file, rc, parallelcopies, instr);
+ return get_reg(ctx, reg_file, temp, parallelcopies, instr);
}
//FIXME: if nothing helps, shift-rotate the registers to make space
unreachable("did not find a register");
}
-
-std::pair<PhysReg, bool> get_reg_vec(ra_ctx& ctx,
- RegisterFile& reg_file,
- RegClass rc)
-{
- uint32_t size = rc.size();
- uint32_t stride = 1;
- uint32_t lb, ub;
- if (rc.type() == RegType::vgpr) {
- lb = 256;
- ub = 256 + ctx.program->max_reg_demand.vgpr;
- } else {
- lb = 0;
- ub = ctx.program->max_reg_demand.sgpr;
- if (size == 2)
- stride = 2;
- else if (size >= 4)
- stride = 4;
- }
- return get_reg_simple(ctx, reg_file, lb, ub, size, stride, rc);
-}
-
-
PhysReg get_reg_create_vector(ra_ctx& ctx,
RegisterFile& reg_file,
- RegClass rc,
+ Temp temp,
std::vector<std::pair<Operand, Definition>>& parallelcopies,
aco_ptr<Instruction>& instr)
{
+ RegClass rc = temp.regClass();
/* create_vector instructions have different costs w.r.t. register coalescing */
uint32_t size = rc.size();
+ uint32_t bytes = rc.bytes();
uint32_t stride = 1;
uint32_t lb, ub;
if (rc.type() == RegType::vgpr) {
stride = 4;
}
+ //TODO: improve p_create_vector for sub-dword vectors
+
unsigned best_pos = -1;
unsigned num_moves = 0xFF;
bool best_war_hint = true;
/* test for each operand which definition placement causes the least shuffle instructions */
- for (unsigned i = 0, offset = 0; i < instr->operands.size(); offset += instr->operands[i].size(), i++) {
+ for (unsigned i = 0, offset = 0; i < instr->operands.size(); offset += instr->operands[i].bytes(), i++) {
// TODO: think about, if we can alias live operands on the same register
if (!instr->operands[i].isTemp() || !instr->operands[i].isKillBeforeDef() || instr->operands[i].getTemp().type() != rc.type())
continue;
- if (offset > instr->operands[i].physReg())
+ if (offset > instr->operands[i].physReg().reg_b)
continue;
- unsigned reg_lo = instr->operands[i].physReg() - offset;
+ unsigned reg_lo = instr->operands[i].physReg().reg_b - offset;
+ if (reg_lo % 4)
+ continue;
+ reg_lo /= 4;
unsigned reg_hi = reg_lo + size - 1;
unsigned k = 0;
bool linear_vgpr = false;
for (unsigned j = reg_lo; j <= reg_hi && !linear_vgpr; j++) {
if (reg_file[j] != 0) {
- k++;
- /* we cannot split live ranges of linear vgprs */
- if (ctx.assignments[reg_file[j]].rc & (1 << 6))
- linear_vgpr = true;
+ if (reg_file[j] == 0xF0000000) {
+ PhysReg reg;
+ reg.reg_b = j * 4;
+ unsigned bytes_left = bytes - (j - reg_lo) * 4;
+ for (unsigned k = 0; k < MIN2(bytes_left, 4); k++, reg.reg_b++)
+ k += reg_file.test(reg, 1);
+ } else {
+ k += 4;
+ /* we cannot split live ranges of linear vgprs */
+ if (ctx.assignments[reg_file[j]].rc & (1 << 6))
+ linear_vgpr = true;
+ }
}
war_hint |= ctx.war_hint[j];
}
continue;
/* count operands in wrong positions */
- for (unsigned j = 0, offset = 0; j < instr->operands.size(); offset += instr->operands[j].size(), j++) {
+ for (unsigned j = 0, offset = 0; j < instr->operands.size(); offset += instr->operands[j].bytes(), j++) {
if (j == i ||
!instr->operands[j].isTemp() ||
instr->operands[j].getTemp().type() != rc.type())
continue;
- if (instr->operands[j].physReg() != reg_lo + offset)
- k += instr->operands[j].size();
+ if (instr->operands[j].physReg().reg_b != reg_lo * 4 + offset)
+ k += instr->operands[j].bytes();
}
bool aligned = rc == RegClass::v4 && reg_lo % 4 == 0;
if (k > num_moves || (!aligned && k == num_moves))
best_war_hint = war_hint;
}
- if (num_moves >= size)
- return get_reg(ctx, reg_file, rc, parallelcopies, instr);
+ if (num_moves >= bytes)
+ return get_reg(ctx, reg_file, temp, parallelcopies, instr);
/* collect variables to be moved */
std::set<std::pair<unsigned, unsigned>> vars = collect_vars(ctx, reg_file, PhysReg{best_pos}, size);
/* move killed operands which aren't yet at the correct position */
- for (unsigned i = 0, offset = 0; i < instr->operands.size(); offset += instr->operands[i].size(), i++) {
+ uint64_t moved_operand_mask = 0;
+ for (unsigned i = 0, offset = 0; i < instr->operands.size(); offset += instr->operands[i].bytes(), i++) {
if (instr->operands[i].isTemp() &&
instr->operands[i].isFirstKillBeforeDef() &&
instr->operands[i].getTemp().type() == rc.type() &&
- instr->operands[i].physReg() != best_pos + offset)
+ instr->operands[i].physReg().reg_b != best_pos * 4 + offset) {
vars.emplace(instr->operands[i].bytes(), instr->operands[i].tempId());
+ moved_operand_mask |= (uint64_t)1 << i;
+ }
}
ASSERTED bool success = false;
update_renames(ctx, reg_file, parallelcopies, instr);
adjust_max_used_regs(ctx, rc, best_pos);
- return PhysReg{best_pos};
-}
-
-bool get_reg_specified(ra_ctx& ctx,
- RegisterFile& reg_file,
- RegClass rc,
- std::vector<std::pair<Operand, Definition>>& parallelcopies,
- aco_ptr<Instruction>& instr,
- PhysReg reg)
-{
- uint32_t size = rc.size();
- uint32_t stride = 1;
- uint32_t lb, ub;
- if (rc.type() == RegType::vgpr) {
- lb = 256;
- ub = 256 + ctx.program->max_reg_demand.vgpr;
- } else {
- if (size == 2)
- stride = 2;
- else if (size >= 4)
- stride = 4;
- if (reg % stride != 0)
- return false;
- lb = 0;
- ub = ctx.program->max_reg_demand.sgpr;
+ while (moved_operand_mask) {
+ unsigned i = u_bit_scan64(&moved_operand_mask);
+ assert(instr->operands[i].isFirstKillBeforeDef());
+ reg_file.clear(instr->operands[i]);
}
- if (rc.is_subdword() && reg.byte() && !instr_can_access_subdword(instr))
- return false;
-
- uint32_t reg_lo = reg.reg();
- uint32_t reg_hi = reg + (size - 1);
-
- if (reg_lo < lb || reg_hi >= ub || reg_lo > reg_hi)
- return false;
-
- if (reg_file.test(reg, rc.bytes()))
- return false;
-
- adjust_max_used_regs(ctx, rc, reg_lo);
- return true;
+ return PhysReg{best_pos};
}
void handle_pseudo(ra_ctx& ctx,
bool operand_can_use_reg(aco_ptr<Instruction>& instr, unsigned idx, PhysReg reg)
{
+ if (instr->operands[idx].isFixed())
+ return instr->operands[idx].physReg() == reg;
+
if (!instr_can_access_subdword(instr) && reg.byte())
return false;
}
}
-} /* end namespace */
+void get_reg_for_operand(ra_ctx& ctx, RegisterFile& register_file,
+ std::vector<std::pair<Operand, Definition>>& parallelcopy,
+ aco_ptr<Instruction>& instr, Operand& operand)
+{
+ /* check if the operand is fixed */
+ PhysReg dst;
+ if (operand.isFixed()) {
+ assert(operand.physReg() != ctx.assignments[operand.tempId()].reg);
+
+ /* check if target reg is blocked, and move away the blocking var */
+ if (register_file[operand.physReg().reg()]) {
+ assert(register_file[operand.physReg()] != 0xF0000000);
+ uint32_t blocking_id = register_file[operand.physReg().reg()];
+ RegClass rc = ctx.assignments[blocking_id].rc;
+ Operand pc_op = Operand(Temp{blocking_id, rc});
+ pc_op.setFixed(operand.physReg());
+
+ /* find free reg */
+ PhysReg reg = get_reg(ctx, register_file, pc_op.getTemp(), parallelcopy, ctx.pseudo_dummy);
+ Definition pc_def = Definition(PhysReg{reg}, pc_op.regClass());
+ register_file.clear(pc_op);
+ parallelcopy.emplace_back(pc_op, pc_def);
+ }
+ dst = operand.physReg();
+ } else {
+ dst = get_reg(ctx, register_file, operand.getTemp(), parallelcopy, instr);
+ }
-void register_allocation(Program *program, std::vector<std::set<Temp>> live_out_per_block)
-{
- ra_ctx ctx(program);
+ Operand pc_op = operand;
+ pc_op.setFixed(ctx.assignments[operand.tempId()].reg);
+ Definition pc_def = Definition(dst, pc_op.regClass());
+ register_file.clear(pc_op);
+ parallelcopy.emplace_back(pc_op, pc_def);
+ update_renames(ctx, register_file, parallelcopy, instr);
+}
- std::vector<std::unordered_map<unsigned, Temp>> renames(program->blocks.size());
-
- struct phi_info {
- Instruction* phi;
- unsigned block_idx;
- std::set<Instruction*> uses;
- };
-
- bool filled[program->blocks.size()];
- bool sealed[program->blocks.size()];
- memset(filled, 0, sizeof filled);
- memset(sealed, 0, sizeof sealed);
- std::vector<std::vector<Instruction*>> incomplete_phis(program->blocks.size());
- std::map<unsigned, phi_info> phi_map;
- std::map<unsigned, unsigned> affinities;
- std::function<Temp(Temp,unsigned)> read_variable;
- std::function<Temp(Temp,Block*)> handle_live_in;
- std::function<Temp(std::map<unsigned, phi_info>::iterator)> try_remove_trivial_phi;
-
- read_variable = [&](Temp val, unsigned block_idx) -> Temp {
- std::unordered_map<unsigned, Temp>::iterator it = renames[block_idx].find(val.id());
- assert(it != renames[block_idx].end());
+Temp read_variable(ra_ctx& ctx, Temp val, unsigned block_idx)
+{
+ std::unordered_map<unsigned, Temp>::iterator it = ctx.renames[block_idx].find(val.id());
+ if (it == ctx.renames[block_idx].end())
+ return val;
+ else
return it->second;
- };
+}
- handle_live_in = [&](Temp val, Block *block) -> Temp {
- std::vector<unsigned>& preds = val.is_linear() ? block->linear_preds : block->logical_preds;
- if (preds.size() == 0 || val.regClass() == val.regClass().as_linear()) {
- renames[block->index][val.id()] = val;
- return val;
+Temp handle_live_in(ra_ctx& ctx, Temp val, Block* block)
+{
+ std::vector<unsigned>& preds = val.is_linear() ? block->linear_preds : block->logical_preds;
+ if (preds.size() == 0 || val.regClass() == val.regClass().as_linear())
+ return val;
+
+ assert(preds.size() > 0);
+
+ Temp new_val;
+ if (!ctx.sealed[block->index]) {
+ /* consider rename from already processed predecessor */
+ Temp tmp = read_variable(ctx, val, preds[0]);
+
+ /* if the block is not sealed yet, we create an incomplete phi (which might later get removed again) */
+ new_val = Temp{ctx.program->allocateId(), val.regClass()};
+ ctx.assignments.emplace_back();
+ aco_opcode opcode = val.is_linear() ? aco_opcode::p_linear_phi : aco_opcode::p_phi;
+ aco_ptr<Instruction> phi{create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, preds.size(), 1)};
+ phi->definitions[0] = Definition(new_val);
+ for (unsigned i = 0; i < preds.size(); i++)
+ phi->operands[i] = Operand(val);
+ if (tmp.regClass() == new_val.regClass())
+ ctx.affinities[new_val.id()] = tmp.id();
+
+ ctx.phi_map.emplace(new_val.id(), phi_info{phi.get(), block->index});
+ ctx.incomplete_phis[block->index].emplace_back(phi.get());
+ block->instructions.insert(block->instructions.begin(), std::move(phi));
+
+ } else if (preds.size() == 1) {
+ /* if the block has only one predecessor, just look there for the name */
+ new_val = read_variable(ctx, val, preds[0]);
+ } else {
+ /* there are multiple predecessors and the block is sealed */
+ Temp ops[preds.size()];
+
+ /* get the rename from each predecessor and check if they are the same */
+ bool needs_phi = false;
+ for (unsigned i = 0; i < preds.size(); i++) {
+ ops[i] = read_variable(ctx, val, preds[i]);
+ if (i == 0)
+ new_val = ops[i];
+ else
+ needs_phi |= !(new_val == ops[i]);
}
- assert(preds.size() > 0);
- Temp new_val;
- if (!sealed[block->index]) {
- /* consider rename from already processed predecessor */
- Temp tmp = read_variable(val, preds[0]);
-
- /* if the block is not sealed yet, we create an incomplete phi (which might later get removed again) */
- new_val = Temp{program->allocateId(), val.regClass()};
- ctx.assignments.emplace_back();
+ if (needs_phi) {
+ /* the variable has been renamed differently in the predecessors: we need to insert a phi */
aco_opcode opcode = val.is_linear() ? aco_opcode::p_linear_phi : aco_opcode::p_phi;
aco_ptr<Instruction> phi{create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, preds.size(), 1)};
+ new_val = Temp{ctx.program->allocateId(), val.regClass()};
phi->definitions[0] = Definition(new_val);
- for (unsigned i = 0; i < preds.size(); i++)
- phi->operands[i] = Operand(val);
- if (tmp.regClass() == new_val.regClass())
- affinities[new_val.id()] = tmp.id();
-
- phi_map.emplace(new_val.id(), phi_info{phi.get(), block->index});
- incomplete_phis[block->index].emplace_back(phi.get());
+ for (unsigned i = 0; i < preds.size(); i++) {
+ phi->operands[i] = Operand(ops[i]);
+ phi->operands[i].setFixed(ctx.assignments[ops[i].id()].reg);
+ if (ops[i].regClass() == new_val.regClass())
+ ctx.affinities[new_val.id()] = ops[i].id();
+ }
+ ctx.assignments.emplace_back();
+ assert(ctx.assignments.size() == ctx.program->peekAllocationId());
+ ctx.phi_map.emplace(new_val.id(), phi_info{phi.get(), block->index});
block->instructions.insert(block->instructions.begin(), std::move(phi));
+ }
+ }
- } else if (preds.size() == 1) {
- /* if the block has only one predecessor, just look there for the name */
- new_val = read_variable(val, preds[0]);
- } else {
- /* there are multiple predecessors and the block is sealed */
- Temp ops[preds.size()];
+ if (new_val != val) {
+ ctx.renames[block->index][val.id()] = new_val;
+ ctx.orig_names[new_val.id()] = val;
+ }
+ return new_val;
+}
- /* we start assuming that the name is the same from all predecessors */
- renames[block->index][val.id()] = val;
- bool needs_phi = false;
+void try_remove_trivial_phi(ra_ctx& ctx, Temp temp)
+{
+ std::unordered_map<unsigned, phi_info>::iterator info = ctx.phi_map.find(temp.id());
- /* get the rename from each predecessor and check if they are the same */
- for (unsigned i = 0; i < preds.size(); i++) {
- ops[i] = read_variable(val, preds[i]);
- if (i == 0)
- new_val = ops[i];
- else
- needs_phi |= !(new_val == ops[i]);
- }
+ if (info == ctx.phi_map.end() || !ctx.sealed[info->second.block_idx])
+ return;
- if (needs_phi) {
- /* the variable has been renamed differently in the predecessors: we need to insert a phi */
- aco_opcode opcode = val.is_linear() ? aco_opcode::p_linear_phi : aco_opcode::p_phi;
- aco_ptr<Instruction> phi{create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, preds.size(), 1)};
- new_val = Temp{program->allocateId(), val.regClass()};
- phi->definitions[0] = Definition(new_val);
- for (unsigned i = 0; i < preds.size(); i++) {
- phi->operands[i] = Operand(ops[i]);
- phi->operands[i].setFixed(ctx.assignments[ops[i].id()].reg);
- if (ops[i].regClass() == new_val.regClass())
- affinities[new_val.id()] = ops[i].id();
- }
- ctx.assignments.emplace_back();
- assert(ctx.assignments.size() == ctx.program->peekAllocationId());
- phi_map.emplace(new_val.id(), phi_info{phi.get(), block->index});
- block->instructions.insert(block->instructions.begin(), std::move(phi));
- }
+ assert(info->second.block_idx != 0);
+ Instruction* phi = info->second.phi;
+ Temp same = Temp();
+ Definition def = phi->definitions[0];
+
+ /* a phi node is trivial if all operands are the same as the definition of the phi */
+ for (const Operand& op : phi->operands) {
+ const Temp t = op.getTemp();
+ if (t == same || t == def.getTemp()) {
+ assert(t == same || op.physReg() == def.physReg());
+ continue;
}
+ if (same != Temp())
+ return;
- renames[block->index][val.id()] = new_val;
- renames[block->index][new_val.id()] = new_val;
- ctx.orig_names[new_val.id()] = val;
- return new_val;
- };
-
- try_remove_trivial_phi = [&] (std::map<unsigned, phi_info>::iterator info) -> Temp {
- assert(info->second.block_idx != 0);
- Instruction* phi = info->second.phi;
- Temp same = Temp();
-
- Definition def = phi->definitions[0];
- /* a phi node is trivial if all operands are the same as the definition of the phi */
- for (const Operand& op : phi->operands) {
- const Temp t = op.getTemp();
- if (t == same || t == def.getTemp())
+ same = t;
+ }
+ assert(same != Temp() || same == def.getTemp());
+
+ /* reroute all uses to same and remove phi */
+ std::vector<Temp> phi_users;
+ std::unordered_map<unsigned, phi_info>::iterator same_phi_info = ctx.phi_map.find(same.id());
+ for (Instruction* instr : info->second.uses) {
+ assert(phi != instr);
+ /* recursively try to remove trivial phis */
+ if (is_phi(instr)) {
+ /* ignore if the phi was already flagged trivial */
+ if (instr->definitions.empty())
continue;
- if (!(same == Temp()) || !(op.physReg() == def.physReg())) {
- /* phi is not trivial */
- return def.getTemp();
- }
- same = t;
- }
- assert(!(same == Temp() || same == def.getTemp()));
-
- /* reroute all uses to same and remove phi */
- std::vector<std::map<unsigned, phi_info>::iterator> phi_users;
- std::map<unsigned, phi_info>::iterator same_phi_info = phi_map.find(same.id());
- for (Instruction* instr : info->second.uses) {
- assert(phi != instr);
- /* recursively try to remove trivial phis */
- if (is_phi(instr)) {
- /* ignore if the phi was already flagged trivial */
- if (instr->definitions.empty())
- continue;
- std::map<unsigned, phi_info>::iterator it = phi_map.find(instr->definitions[0].tempId());
- if (it != phi_map.end() && it != info)
- phi_users.emplace_back(it);
- }
- for (Operand& op : instr->operands) {
- if (op.isTemp() && op.tempId() == def.tempId()) {
- op.setTemp(same);
- if (same_phi_info != phi_map.end())
- same_phi_info->second.uses.emplace(instr);
- }
+ if (instr->definitions[0].getTemp() != temp)
+ phi_users.emplace_back(instr->definitions[0].getTemp());
+ }
+ for (Operand& op : instr->operands) {
+ if (op.isTemp() && op.tempId() == def.tempId()) {
+ op.setTemp(same);
+ if (same_phi_info != ctx.phi_map.end())
+ same_phi_info->second.uses.emplace(instr);
}
}
+ }
- auto it = ctx.orig_names.find(same.id());
- unsigned orig_var = it != ctx.orig_names.end() ? it->second.id() : same.id();
- for (unsigned i = 0; i < program->blocks.size(); i++) {
- auto it = renames[i].find(orig_var);
- if (it != renames[i].end() && it->second == def.getTemp())
- renames[i][orig_var] = same;
- }
+ auto it = ctx.orig_names.find(same.id());
+ unsigned orig_var = it != ctx.orig_names.end() ? it->second.id() : same.id();
+ for (unsigned i = 0; i < ctx.program->blocks.size(); i++) {
+ auto it = ctx.renames[i].find(orig_var);
+ if (it != ctx.renames[i].end() && it->second == def.getTemp())
+ ctx.renames[i][orig_var] = same;
+ }
- unsigned block_idx = info->second.block_idx;
- phi->definitions.clear(); /* this indicates that the phi can be removed */
- phi_map.erase(info);
- for (auto it : phi_users) {
- if (sealed[it->second.block_idx])
- try_remove_trivial_phi(it);
- }
+ phi->definitions.clear(); /* this indicates that the phi can be removed */
+ ctx.phi_map.erase(info);
+ for (Temp t : phi_users)
+ try_remove_trivial_phi(ctx, t);
- /* due to the removal of other phis, the name might have changed once again! */
- return renames[block_idx][orig_var];
- };
+ return;
+}
- std::map<unsigned, Instruction*> vectors;
+} /* end namespace */
+
+
+void register_allocation(Program *program, std::vector<TempSet>& live_out_per_block)
+{
+ ra_ctx ctx(program);
std::vector<std::vector<Temp>> phi_ressources;
- std::map<unsigned, unsigned> temp_to_phi_ressources;
+ std::unordered_map<unsigned, unsigned> temp_to_phi_ressources;
for (std::vector<Block>::reverse_iterator it = program->blocks.rbegin(); it != program->blocks.rend(); it++) {
Block& block = *it;
/* first, compute the death points of all live vars within the block */
- std::set<Temp>& live = live_out_per_block[block.index];
+ TempSet& live = live_out_per_block[block.index];
std::vector<aco_ptr<Instruction>>::reverse_iterator rit;
for (rit = block.instructions.rbegin(); rit != block.instructions.rend(); ++rit) {
/* add vector affinities */
if (instr->opcode == aco_opcode::p_create_vector) {
for (const Operand& op : instr->operands) {
- if (op.isTemp() && op.getTemp().type() == instr->definitions[0].getTemp().type())
- vectors[op.tempId()] = instr.get();
+ if (op.isTemp() && op.isFirstKill() && op.getTemp().type() == instr->definitions[0].getTemp().type())
+ ctx.vectors[op.tempId()] = instr.get();
}
}
continue;
live.erase(def.getTemp());
/* mark last-seen phi operand */
- std::map<unsigned, unsigned>::iterator it = temp_to_phi_ressources.find(def.tempId());
+ std::unordered_map<unsigned, unsigned>::iterator it = temp_to_phi_ressources.find(def.tempId());
if (it != temp_to_phi_ressources.end() && def.regClass() == phi_ressources[it->second][0].regClass()) {
phi_ressources[it->second][0] = def.getTemp();
/* try to coalesce phi affinities with parallelcopies */
assert(vec.size() > 1);
for (unsigned i = 1; i < vec.size(); i++)
if (vec[i].id() != vec[0].id())
- affinities[vec[i].id()] = vec[0].id();
+ ctx.affinities[vec[i].id()] = vec[0].id();
}
/* state of register file after phis */
std::vector<std::bitset<128>> sgpr_live_in(program->blocks.size());
for (Block& block : program->blocks) {
- std::set<Temp>& live = live_out_per_block[block.index];
+ TempSet& live = live_out_per_block[block.index];
/* initialize register file */
assert(block.index != 0 || live.empty());
RegisterFile register_file;
ctx.war_hint.reset();
for (Temp t : live) {
- Temp renamed = handle_live_in(t, &block);
- if (ctx.assignments[renamed.id()].assigned)
- register_file.fill(ctx.assignments[renamed.id()].reg, t.size(), renamed.id());
+ Temp renamed = handle_live_in(ctx, t, &block);
+ assignment& var = ctx.assignments[renamed.id()];
+ /* due to live-range splits, the live-in might be a phi, now */
+ if (var.assigned)
+ register_file.fill(Definition(renamed.id(), var.reg, var.rc));
}
std::vector<aco_ptr<Instruction>> instructions;
if (definition.isKill() || definition.isFixed())
continue;
- if (affinities.find(definition.tempId()) != affinities.end() &&
- ctx.assignments[affinities[definition.tempId()]].assigned) {
- assert(ctx.assignments[affinities[definition.tempId()]].rc == definition.regClass());
- PhysReg reg = ctx.assignments[affinities[definition.tempId()]].reg;
+ if (ctx.affinities.find(definition.tempId()) != ctx.affinities.end() &&
+ ctx.assignments[ctx.affinities[definition.tempId()]].assigned) {
+ assert(ctx.assignments[ctx.affinities[definition.tempId()]].rc == definition.regClass());
+ PhysReg reg = ctx.assignments[ctx.affinities[definition.tempId()]].reg;
bool try_use_special_reg = reg == scc || reg == exec;
if (try_use_special_reg) {
for (const Operand& op : phi->operands) {
if (definition.isKill())
continue;
- renames[block.index][definition.tempId()] = definition.getTemp();
-
if (!definition.isFixed()) {
std::vector<std::pair<Operand, Definition>> parallelcopy;
/* try to find a register that is used by at least one operand */
}
}
if (!definition.isFixed())
- definition.setFixed(get_reg(ctx, register_file, definition.regClass(), parallelcopy, phi));
+ definition.setFixed(get_reg(ctx, register_file, definition.getTemp(), parallelcopy, phi));
/* process parallelcopy */
for (std::pair<Operand, Definition> pc : parallelcopy) {
}
if (prev_phi) {
/* if so, just update that phi's register */
+ register_file.clear(prev_phi->definitions[0]);
prev_phi->definitions[0].setFixed(pc.second.physReg());
ctx.assignments[prev_phi->definitions[0].tempId()] = {pc.second.physReg(), pc.second.regClass()};
- register_file.fill(pc.second.physReg(), pc.second.size(), prev_phi->definitions[0].tempId());
+ register_file.fill(prev_phi->definitions[0]);
continue;
}
/* rename */
- std::map<unsigned, Temp>::iterator orig_it = ctx.orig_names.find(pc.first.tempId());
+ std::unordered_map<unsigned, Temp>::iterator orig_it = ctx.orig_names.find(pc.first.tempId());
Temp orig = pc.first.getTemp();
if (orig_it != ctx.orig_names.end())
orig = orig_it->second;
else
ctx.orig_names[pc.second.tempId()] = orig;
- renames[block.index][orig.id()] = pc.second.getTemp();
- renames[block.index][pc.second.tempId()] = pc.second.getTemp();
+ ctx.renames[block.index][orig.id()] = pc.second.getTemp();
/* otherwise, this is a live-in and we need to create a new phi
* to move it in this block's predecessors */
/* update phi affinities */
for (const Operand& op : phi->operands) {
if (op.isTemp() && op.regClass() == phi->definitions[0].regClass())
- affinities[op.tempId()] = definition.tempId();
+ ctx.affinities[op.tempId()] = definition.tempId();
}
instructions.emplace_back(std::move(*it));
if (phi->operands[idx].isTemp() &&
phi->operands[idx].getTemp().type() == RegType::sgpr &&
phi->operands[idx].isFirstKillBeforeDef()) {
- Temp phi_op = read_variable(phi->operands[idx].getTemp(), block.index);
+ Temp phi_op = read_variable(ctx, phi->operands[idx].getTemp(), block.index);
PhysReg reg = ctx.assignments[phi_op.id()].reg;
assert(register_file[reg] == phi_op.id());
register_file[reg] = 0;
continue;
/* rename operands */
- operand.setTemp(read_variable(operand.getTemp(), block.index));
-
- /* check if the operand is fixed */
- if (operand.isFixed()) {
-
- if (operand.physReg() == ctx.assignments[operand.tempId()].reg) {
- /* we are fine: the operand is already assigned the correct reg */
-
- } else {
- /* check if target reg is blocked, and move away the blocking var */
- if (register_file[operand.physReg().reg()]) {
- uint32_t blocking_id = register_file[operand.physReg().reg()];
- RegClass rc = ctx.assignments[blocking_id].rc;
- Operand pc_op = Operand(Temp{blocking_id, rc});
- pc_op.setFixed(operand.physReg());
- Definition pc_def = Definition(Temp{program->allocateId(), pc_op.regClass()});
- /* find free reg */
- PhysReg reg = get_reg(ctx, register_file, pc_op.regClass(), parallelcopy, instr);
- pc_def.setFixed(reg);
- ctx.assignments.emplace_back(reg, pc_def.regClass());
- assert(ctx.assignments.size() == ctx.program->peekAllocationId());
- register_file.clear(pc_op);
- register_file.fill(pc_def);
- parallelcopy.emplace_back(pc_op, pc_def);
-
- /* handle renames of previous operands */
- for (unsigned j = 0; j < i; j++) {
- Operand& op = instr->operands[j];
- if (op.isTemp() && op.tempId() == blocking_id) {
- op.setTemp(pc_def.getTemp());
- op.setFixed(reg);
- }
- }
- }
- /* move operand to fixed reg and create parallelcopy pair */
- Operand pc_op = operand;
- Temp tmp = Temp{program->allocateId(), operand.regClass()};
- Definition pc_def = Definition(tmp);
- pc_def.setFixed(operand.physReg());
- pc_op.setFixed(ctx.assignments[operand.tempId()].reg);
- operand.setTemp(tmp);
- ctx.assignments.emplace_back(pc_def.physReg(), pc_def.regClass());
- assert(ctx.assignments.size() == ctx.program->peekAllocationId());
- operand.setFixed(pc_def.physReg());
- register_file.clear(pc_op);
- register_file.fill(pc_def);
- parallelcopy.emplace_back(pc_op, pc_def);
- }
- } else {
- assert(ctx.assignments[operand.tempId()].assigned);
- PhysReg reg = ctx.assignments[operand.tempId()].reg;
+ operand.setTemp(read_variable(ctx, operand.getTemp(), block.index));
+ assert(ctx.assignments[operand.tempId()].assigned);
- if (operand_can_use_reg(instr, i, reg)) {
- operand.setFixed(ctx.assignments[operand.tempId()].reg);
- } else {
- Operand pc_op = operand;
- pc_op.setFixed(reg);
- PhysReg new_reg = get_reg(ctx, register_file, operand.regClass(), parallelcopy, instr);
- Definition pc_def = Definition(program->allocateId(), new_reg, pc_op.regClass());
- ctx.assignments.emplace_back(new_reg, pc_def.regClass());
- assert(ctx.assignments.size() == ctx.program->peekAllocationId());
- register_file.clear(pc_op);
- register_file.fill(pc_def);
- parallelcopy.emplace_back(pc_op, pc_def);
- operand.setTemp(pc_def.getTemp());
- operand.setFixed(new_reg);
- }
+ PhysReg reg = ctx.assignments[operand.tempId()].reg;
+ if (operand_can_use_reg(instr, i, reg))
+ operand.setFixed(reg);
+ else
+ get_reg_for_operand(ctx, register_file, parallelcopy, instr, operand);
- if (instr->format == Format::EXP ||
- (instr->isVMEM() && i == 3 && program->chip_class == GFX6) ||
- (instr->format == Format::DS && static_cast<DS_instruction*>(instr.get())->gds)) {
- for (unsigned j = 0; j < operand.size(); j++)
- ctx.war_hint.set(operand.physReg().reg() + j);
- }
+ if (instr->format == Format::EXP ||
+ (instr->isVMEM() && i == 3 && ctx.program->chip_class == GFX6) ||
+ (instr->format == Format::DS && static_cast<DS_instruction*>(instr.get())->gds)) {
+ for (unsigned j = 0; j < operand.size(); j++)
+ ctx.war_hint.set(operand.physReg().reg() + j);
}
- std::map<unsigned, phi_info>::iterator phi = phi_map.find(operand.getTemp().id());
- if (phi != phi_map.end())
- phi->second.uses.emplace(instr.get());
+ std::unordered_map<unsigned, phi_info>::iterator phi = ctx.phi_map.find(operand.getTemp().id());
+ if (phi != ctx.phi_map.end())
+ phi->second.uses.emplace(instr.get());
}
+
/* remove dead vars from register file */
for (const Operand& op : instr->operands) {
if (op.isTemp() && op.isFirstKillBeforeDef())
}
/* find a new register for the blocking variable */
- PhysReg reg = get_reg(ctx, register_file, rc, parallelcopy, instr);
+ PhysReg reg = get_reg(ctx, register_file, pc_op.getTemp(), parallelcopy, instr);
/* once again, disable killed operands */
for (const Operand& op : instr->operands) {
if (op.isTemp() && op.isFirstKillBeforeDef())
live.emplace(definition.getTemp());
ctx.assignments[definition.tempId()] = {definition.physReg(), definition.regClass()};
- renames[block.index][definition.tempId()] = definition.getTemp();
register_file.fill(definition);
}
else if (instr->opcode == aco_opcode::p_split_vector) {
PhysReg reg = instr->operands[0].physReg();
reg.reg_b += i * definition.bytes();
- if (!get_reg_specified(ctx, register_file, definition.regClass(), parallelcopy, instr, reg))
- reg = get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr);
- definition.setFixed(reg);
+ if (get_reg_specified(ctx, register_file, definition.regClass(), parallelcopy, instr, reg))
+ definition.setFixed(reg);
} else if (instr->opcode == aco_opcode::p_wqm) {
PhysReg reg;
if (instr->operands[0].isKillBeforeDef() && instr->operands[0].getTemp().type() == definition.getTemp().type()) {
reg = instr->operands[0].physReg();
+ definition.setFixed(reg);
assert(register_file[reg.reg()] == 0);
- } else {
- reg = get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr);
}
- definition.setFixed(reg);
} else if (instr->opcode == aco_opcode::p_extract_vector) {
PhysReg reg;
if (instr->operands[0].isKillBeforeDef() &&
reg = instr->operands[0].physReg();
reg.reg_b += definition.bytes() * instr->operands[1].constantValue();
assert(!register_file.test(reg, definition.bytes()));
- } else {
- reg = get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr);
+ definition.setFixed(reg);
}
- definition.setFixed(reg);
} else if (instr->opcode == aco_opcode::p_create_vector) {
- PhysReg reg = get_reg_create_vector(ctx, register_file, definition.regClass(),
+ PhysReg reg = get_reg_create_vector(ctx, register_file, definition.getTemp(),
parallelcopy, instr);
definition.setFixed(reg);
- } else if (affinities.find(definition.tempId()) != affinities.end() &&
- ctx.assignments[affinities[definition.tempId()]].assigned) {
- PhysReg reg = ctx.assignments[affinities[definition.tempId()]].reg;
- if (get_reg_specified(ctx, register_file, definition.regClass(), parallelcopy, instr, reg))
- definition.setFixed(reg);
- else
- definition.setFixed(get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr));
+ }
- } else if (vectors.find(definition.tempId()) != vectors.end()) {
- Instruction* vec = vectors[definition.tempId()];
- unsigned byte_offset = 0;
- for (const Operand& op : vec->operands) {
- if (op.isTemp() && op.tempId() == definition.tempId())
- break;
- else
- byte_offset += op.bytes();
- }
- unsigned k = 0;
- for (const Operand& op : vec->operands) {
- if (op.isTemp() &&
- op.tempId() != definition.tempId() &&
- op.getTemp().type() == definition.getTemp().type() &&
- ctx.assignments[op.tempId()].assigned) {
- PhysReg reg = ctx.assignments[op.tempId()].reg;
- reg.reg_b += (byte_offset - k);
- if (get_reg_specified(ctx, register_file, definition.regClass(), parallelcopy, instr, reg)) {
- definition.setFixed(reg);
- break;
- }
- }
- k += op.bytes();
- }
- if (!definition.isFixed()) {
- std::pair<PhysReg, bool> res = get_reg_vec(ctx, register_file, vec->definitions[0].regClass());
- PhysReg reg = res.first;
- if (res.second) {
- reg.reg_b += byte_offset;
- /* make sure to only use byte offset if the instruction supports it */
- if (vec->definitions[0].regClass().is_subdword() && reg.byte() && !instr_can_access_subdword(instr))
- reg = get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr);
- } else {
- reg = get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr);
- }
- definition.setFixed(reg);
+ if (!definition.isFixed()) {
+ Temp tmp = definition.getTemp();
+ /* subdword instructions before RDNA write full registers */
+ if (tmp.regClass().is_subdword() &&
+ !instr_can_access_subdword(instr) &&
+ ctx.program->chip_class <= GFX9) {
+ assert(tmp.bytes() <= 4);
+ tmp = Temp(definition.tempId(), v1);
}
- } else
- definition.setFixed(get_reg(ctx, register_file, definition.regClass(), parallelcopy, instr));
+ definition.setFixed(get_reg(ctx, register_file, tmp, parallelcopy, instr));
+ }
assert(definition.isFixed() && ((definition.getTemp().type() == RegType::vgpr && definition.physReg() >= 256) ||
(definition.getTemp().type() != RegType::vgpr && definition.physReg() < 256)));
live.emplace(definition.getTemp());
ctx.assignments[definition.tempId()] = {definition.physReg(), definition.regClass()};
- renames[block.index][definition.tempId()] = definition.getTemp();
register_file.fill(definition);
}
assert(pc->operands[i].size() == pc->definitions[i].size());
/* it might happen that the operand is already renamed. we have to restore the original name. */
- std::map<unsigned, Temp>::iterator it = ctx.orig_names.find(pc->operands[i].tempId());
+ std::unordered_map<unsigned, Temp>::iterator it = ctx.orig_names.find(pc->operands[i].tempId());
Temp orig = it != ctx.orig_names.end() ? it->second : pc->operands[i].getTemp();
ctx.orig_names[pc->definitions[i].tempId()] = orig;
- renames[block.index][orig.id()] = pc->definitions[i].getTemp();
- renames[block.index][pc->definitions[i].tempId()] = pc->definitions[i].getTemp();
+ ctx.renames[block.index][orig.id()] = pc->definitions[i].getTemp();
- std::map<unsigned, phi_info>::iterator phi = phi_map.find(pc->operands[i].tempId());
- if (phi != phi_map.end())
+ std::unordered_map<unsigned, phi_info>::iterator phi = ctx.phi_map.find(pc->operands[i].tempId());
+ if (phi != ctx.phi_map.end())
phi->second.uses.emplace(pc.get());
}
}
for (const Operand& op : instr->operands) {
if (op.isTemp() && op.isFirstKill())
- register_file.fill(op.physReg(), op.size(), 0xFFFF);
+ register_file.block(op.physReg(), op.bytes());
}
handle_pseudo(ctx, register_file, pc.get());
register_file.clear(def);
for (const Operand& op : instr->operands) {
if (op.isTemp() && op.isFirstKill())
- register_file.fill(op.physReg(), op.size(), 0xFFFF);
+ register_file.block(op.physReg(), op.bytes());
}
- RegClass rc = can_sgpr ? s1 : v1;
- PhysReg reg = get_reg(ctx, register_file, rc, parallelcopy, instr);
- Temp tmp = {program->allocateId(), rc};
- ctx.assignments.emplace_back(reg, rc);
+ Temp tmp = {program->allocateId(), can_sgpr ? s1 : v1};
+ ctx.assignments.emplace_back();
+ PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, instr);
aco_ptr<Instruction> mov;
if (can_sgpr)
instr->operands[i] = operand;
/* keep phi_map up to date */
if (operand.isTemp()) {
- std::map<unsigned, phi_info>::iterator phi = phi_map.find(operand.tempId());
- if (phi != phi_map.end()) {
+ std::unordered_map<unsigned, phi_info>::iterator phi = ctx.phi_map.find(operand.tempId());
+ if (phi != ctx.phi_map.end()) {
phi->second.uses.erase(tmp.get());
phi->second.uses.emplace(instr.get());
}
block.instructions = std::move(instructions);
- filled[block.index] = true;
+ ctx.filled[block.index] = true;
for (unsigned succ_idx : block.linear_succs) {
Block& succ = program->blocks[succ_idx];
/* seal block if all predecessors are filled */
bool all_filled = true;
for (unsigned pred_idx : succ.linear_preds) {
- if (!filled[pred_idx]) {
+ if (!ctx.filled[pred_idx]) {
all_filled = false;
break;
}
}
if (all_filled) {
+ ctx.sealed[succ_idx] = true;
+
/* finish incomplete phis and check if they became trivial */
- for (Instruction* phi : incomplete_phis[succ_idx]) {
+ for (Instruction* phi : ctx.incomplete_phis[succ_idx]) {
std::vector<unsigned> preds = phi->definitions[0].getTemp().is_linear() ? succ.linear_preds : succ.logical_preds;
for (unsigned i = 0; i < phi->operands.size(); i++) {
- phi->operands[i].setTemp(read_variable(phi->operands[i].getTemp(), preds[i]));
+ phi->operands[i].setTemp(read_variable(ctx, phi->operands[i].getTemp(), preds[i]));
phi->operands[i].setFixed(ctx.assignments[phi->operands[i].tempId()].reg);
}
- try_remove_trivial_phi(phi_map.find(phi->definitions[0].tempId()));
+ try_remove_trivial_phi(ctx, phi->definitions[0].getTemp());
}
/* complete the original phi nodes, but no need to check triviality */
for (aco_ptr<Instruction>& instr : succ.instructions) {
auto& operand = instr->operands[i];
if (!operand.isTemp())
continue;
- operand.setTemp(read_variable(operand.getTemp(), preds[i]));
+ operand.setTemp(read_variable(ctx, operand.getTemp(), preds[i]));
operand.setFixed(ctx.assignments[operand.tempId()].reg);
- std::map<unsigned, phi_info>::iterator phi = phi_map.find(operand.getTemp().id());
- if (phi != phi_map.end())
+ std::unordered_map<unsigned, phi_info>::iterator phi = ctx.phi_map.find(operand.getTemp().id());
+ if (phi != ctx.phi_map.end())
phi->second.uses.emplace(instr.get());
}
}
- sealed[succ_idx] = true;
}
}
} /* end for BB */