ac/llvm: fix amdgcn.rcp for v2f16

[mesa.git] / src / amd / compiler / aco_scheduler.cpp

diff --git a/src/amd/compiler/aco_scheduler.cpp b/src/amd/compiler/aco_scheduler.cpp
index 40941e4c539c6bae159bdc4c7e47b52df6756134..9d6810672b58f776e217a903a1fe50635d86b653 100644 (file)
--- a/src/amd/compiler/aco_scheduler.cpp
+++ b/src/amd/compiler/aco_scheduler.cpp
@@ -459,7 +459,8 @@ HazardResult perform_hazard_query(hazard_query *query, Instruction *instr, bool
    /* don't move non-reorderable instructions */
    if (instr->opcode == aco_opcode::s_memtime ||
        instr->opcode == aco_opcode::s_memrealtime ||
-       instr->opcode == aco_opcode::s_setprio)
+       instr->opcode == aco_opcode::s_setprio ||
+       instr->opcode == aco_opcode::s_getreg_b32)
       return hazard_fail_unreorderable;
 
    memory_event_set instr_set;
@@ -494,6 +495,12 @@ HazardResult perform_hazard_query(hazard_query *query, Instruction *instr, bool
    if (first->bar_classes && second->bar_classes)
       return hazard_fail_barrier;
 
+   /* Don't move memory accesses to before control barriers. I don't think
+    * this is necessary for the Vulkan memory model, but it might be for GLSL450. */
+   unsigned control_classes = storage_buffer | storage_atomic_counter | storage_image | storage_shared;
+   if (first->has_control_barrier && ((second->access_atomic | second->access_relaxed) & control_classes))
+      return hazard_fail_barrier;
+
    /* don't move memory loads/stores past potentially aliasing loads/stores */
    unsigned aliasing_storage = instr->format == Format::SMEM ?
                                query->aliasing_storage_smem :