if (instr->isVOP3()) {
VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
- check((vop3->opsel & ~(0x10 | ((1 << instr->operands.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr.get());
- for (unsigned i = 0; i < instr->operands.size(); i++) {
- if (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed())
- check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for sub-dword operand", instr.get());
+ for (unsigned i = 0; i < 3; i++) {
+ if (i >= instr->operands.size() ||
+ (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
+ check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
}
if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed())
check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get());
if (instr->isSDWA())
scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
- check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
- (int) instr->format & (int) Format::VOPC ||
- instr->opcode == aco_opcode::v_readfirstlane_b32 ||
- instr->opcode == aco_opcode::v_readlane_b32 ||
- instr->opcode == aco_opcode::v_readlane_b32_e64,
- "Wrong Definition type for VALU instruction", instr.get());
+ if ((int) instr->format & (int) Format::VOPC ||
+ instr->opcode == aco_opcode::v_readfirstlane_b32 ||
+ instr->opcode == aco_opcode::v_readlane_b32 ||
+ instr->opcode == aco_opcode::v_readlane_b32_e64) {
+ check(instr->definitions[0].getTemp().type() == RegType::sgpr,
+ "Wrong Definition type for VALU instruction", instr.get());
+ } else {
+ check(instr->definitions[0].getTemp().type() == RegType::vgpr,
+ "Wrong Definition type for VALU instruction", instr.get());
+ }
+
unsigned num_sgprs = 0;
unsigned sgpr[] = {0, 0};
for (unsigned i = 0; i < instr->operands.size(); i++)
Operand op = instr->operands[i];
if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
instr->opcode == aco_opcode::v_readlane_b32 ||
- instr->opcode == aco_opcode::v_readlane_b32_e64 ||
- instr->opcode == aco_opcode::v_writelane_b32 ||
+ instr->opcode == aco_opcode::v_readlane_b32_e64) {
+ check(i != 1 ||
+ (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
+ op.isConstant(),
+ "Must be a SGPR or a constant", instr.get());
+ check(i == 1 ||
+ (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
+ "Wrong Operand type for VALU instruction", instr.get());
+ continue;
+ }
+
+ if (instr->opcode == aco_opcode::v_writelane_b32 ||
instr->opcode == aco_opcode::v_writelane_b32_e64) {
- check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get());
- check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), "Wrong Operand type for VALU instruction", instr.get());
+ check(i != 2 ||
+ (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
+ "Wrong Operand type for VALU instruction", instr.get());
+ check(i == 2 ||
+ (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
+ op.isConstant(),
+ "Must be a SGPR or a constant", instr.get());
continue;
}
if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {