base_format = Format::VOP2;
else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
base_format = Format::VOPC;
- else if ((uint32_t)base_format & (uint32_t)Format::VINTRP)
- base_format = Format::VINTRP;
+ else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) {
+ if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
+ instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
+ instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
+ instr->opcode == aco_opcode::v_interp_p2_f16) {
+ /* v_interp_*_fp16 are considered VINTRP by the compiler but
+ * they are emitted as VOP3.
+ */
+ base_format = Format::VOP3;
+ } else {
+ base_format = Format::VINTRP;
+ }
+ }
check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
/* check VOP3 modifiers */
instr->opcode != aco_opcode::v_fmac_f16,
"SDWA can't be used with this opcode", instr.get());
}
+
+ for (unsigned i = 0; i < MIN2(instr->operands.size(), 2); i++) {
+ if (instr->operands[i].regClass().is_subdword())
+ check((sdwa->sel[i] & sdwa_asuint) == (sdwa_isra | instr->operands[i].bytes()), "Unexpected SDWA sel for sub-dword operand", instr.get());
+ }
+ if (instr->definitions[0].regClass().is_subdword())
+ check((sdwa->dst_sel & sdwa_asuint) == (sdwa_isra | instr->definitions[0].bytes()), "Unexpected SDWA sel for sub-dword definition", instr.get());
}
/* check opsel */
VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
check((vop3->opsel & ~(0x10 | ((1 << instr->operands.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr.get());
+
+ for (unsigned i = 0; i < instr->operands.size(); i++) {
+ if (instr->operands[i].regClass().is_subdword())
+ check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for sub-dword operand", instr.get());
+ }
+ if (instr->definitions[0].regClass().is_subdword())
+ check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get());
}
/* check for undefs */
/* check subdword definitions */
for (unsigned i = 0; i < instr->definitions.size(); i++) {
if (instr->definitions[i].regClass().is_subdword())
- check(instr->isSDWA() || instr->format == Format::PSEUDO, "Only SDWA and Pseudo instructions can write subdword registers", instr.get());
+ check(instr->format == Format::PSEUDO || instr->definitions[i].bytes() <= 4, "Only Pseudo instructions can write subdword registers larger than 4 bytes", instr.get());
}
if (instr->isSALU() || instr->isVALU()) {
instr->opcode == aco_opcode::v_writelane_b32 ||
instr->opcode == aco_opcode::v_writelane_b32_e64) {
check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get());
- check(i == 1 || (op.isTemp() && op.regClass() == v1), "Wrong Operand type for VALU instruction", instr.get());
+ check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), "Wrong Operand type for VALU instruction", instr.get());
continue;
}
if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
}
} else if (instr->opcode == aco_opcode::p_extract_vector) {
check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
- check(instr->operands[1].constantValue() < instr->operands[0].size(), "Index out of range", instr.get());
+ check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <= instr->operands[0].bytes(), "Index out of range", instr.get());
check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
"Cannot extract SGPR value from VGPR vector", instr.get());
} else if (instr->opcode == aco_opcode::p_parallelcopy) {
return true;
}
+bool validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, unsigned index)
+{
+ Operand op = instr->operands[index];
+ unsigned byte = op.physReg().byte();
+
+ if (instr->format == Format::PSEUDO && chip >= GFX8)
+ return true;
+ if (instr->isSDWA() && (static_cast<SDWA_instruction *>(instr.get())->sel[index] & sdwa_asuint) == (sdwa_isra | op.bytes()))
+ return true;
+ if (byte == 2 && can_use_opsel(chip, instr->opcode, index, 1))
+ return true;
+
+ switch (instr->opcode) {
+ case aco_opcode::v_cvt_f32_ubyte1:
+ if (byte == 1)
+ return true;
+ break;
+ case aco_opcode::v_cvt_f32_ubyte2:
+ if (byte == 2)
+ return true;
+ break;
+ case aco_opcode::v_cvt_f32_ubyte3:
+ if (byte == 3)
+ return true;
+ break;
+ case aco_opcode::ds_write_b8_d16_hi:
+ case aco_opcode::ds_write_b16_d16_hi:
+ if (byte == 2 && index == 1)
+ return true;
+ break;
+ case aco_opcode::buffer_store_byte_d16_hi:
+ case aco_opcode::buffer_store_short_d16_hi:
+ if (byte == 2 && index == 3)
+ return true;
+ break;
+ case aco_opcode::flat_store_byte_d16_hi:
+ case aco_opcode::flat_store_short_d16_hi:
+ case aco_opcode::scratch_store_byte_d16_hi:
+ case aco_opcode::scratch_store_short_d16_hi:
+ case aco_opcode::global_store_byte_d16_hi:
+ case aco_opcode::global_store_short_d16_hi:
+ if (byte == 2 && index == 2)
+ return true;
+ default:
+ break;
+ }
+
+ return byte == 0;
+}
+
+bool validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr)
+{
+ Definition def = instr->definitions[0];
+ unsigned byte = def.physReg().byte();
+
+ if (instr->format == Format::PSEUDO && chip >= GFX8)
+ return true;
+ if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
+ return true;
+ if (byte == 2 && can_use_opsel(chip, instr->opcode, -1, 1))
+ return true;
+
+ switch (instr->opcode) {
+ case aco_opcode::buffer_load_ubyte_d16_hi:
+ case aco_opcode::buffer_load_short_d16_hi:
+ case aco_opcode::flat_load_ubyte_d16_hi:
+ case aco_opcode::flat_load_short_d16_hi:
+ case aco_opcode::scratch_load_ubyte_d16_hi:
+ case aco_opcode::scratch_load_short_d16_hi:
+ case aco_opcode::global_load_ubyte_d16_hi:
+ case aco_opcode::global_load_short_d16_hi:
+ case aco_opcode::ds_read_u8_d16_hi:
+ case aco_opcode::ds_read_u16_d16_hi:
+ return byte == 2;
+ default:
+ break;
+ }
+
+ return byte == 0;
+}
+
+unsigned get_subdword_bytes_written(Program *program, const aco_ptr<Instruction>& instr, unsigned index)
+{
+ chip_class chip = program->chip_class;
+ Definition def = instr->definitions[index];
+
+ if (instr->format == Format::PSEUDO)
+ return chip >= GFX8 ? def.bytes() : def.size() * 4u;
+ if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
+ return def.bytes();
+
+ switch (instr->opcode) {
+ case aco_opcode::buffer_load_ubyte_d16:
+ case aco_opcode::buffer_load_short_d16:
+ case aco_opcode::flat_load_ubyte_d16:
+ case aco_opcode::flat_load_short_d16:
+ case aco_opcode::scratch_load_ubyte_d16:
+ case aco_opcode::scratch_load_short_d16:
+ case aco_opcode::global_load_ubyte_d16:
+ case aco_opcode::global_load_short_d16:
+ case aco_opcode::ds_read_u8_d16:
+ case aco_opcode::ds_read_u16_d16:
+ case aco_opcode::buffer_load_ubyte_d16_hi:
+ case aco_opcode::buffer_load_short_d16_hi:
+ case aco_opcode::flat_load_ubyte_d16_hi:
+ case aco_opcode::flat_load_short_d16_hi:
+ case aco_opcode::scratch_load_ubyte_d16_hi:
+ case aco_opcode::scratch_load_short_d16_hi:
+ case aco_opcode::global_load_ubyte_d16_hi:
+ case aco_opcode::global_load_short_d16_hi:
+ case aco_opcode::ds_read_u8_d16_hi:
+ case aco_opcode::ds_read_u16_d16_hi:
+ return program->sram_ecc_enabled ? 4 : 2;
+ case aco_opcode::v_mad_f16:
+ case aco_opcode::v_mad_u16:
+ case aco_opcode::v_mad_i16:
+ case aco_opcode::v_fma_f16:
+ case aco_opcode::v_div_fixup_f16:
+ case aco_opcode::v_interp_p2_f16:
+ if (chip >= GFX9)
+ return 2;
+ default:
+ break;
+ }
+
+ return MAX2(chip >= GFX10 ? def.bytes() : 4, instr_info.definition_size[(int)instr->opcode] / 8u);
+}
+
} /* end namespace */
bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
- if ((op.getTemp().type() == RegType::vgpr && op.physReg() + op.size() > 256 + program->config->num_vgprs) ||
+ if ((op.getTemp().type() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
(op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
if (op.physReg() == vcc && !program->needs_vcc)
err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
- if (!(instr->isSDWA() || instr->format == Format::PSEUDO) && op.regClass().is_subdword() && op.physReg().byte())
- err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d must be aligned to a full register", i);
+ if (op.regClass().is_subdword() && !validate_subdword_operand(program->chip_class, instr, i))
+ err |= ra_fail(output, loc, Location(), "Operand %d not aligned correctly", i);
if (!assignments[op.tempId()].firstloc.block)
assignments[op.tempId()].firstloc = loc;
if (!assignments[op.tempId()].defloc.block)
err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
if (assignments[def.tempId()].defloc.block)
err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
- if ((def.getTemp().type() == RegType::vgpr && def.physReg() + def.size() > 256 + program->config->num_vgprs) ||
+ if ((def.getTemp().type() == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) ||
(def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
if (def.physReg() == vcc && !program->needs_vcc)
err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
+ if (def.regClass().is_subdword() && !validate_subdword_definition(program->chip_class, instr))
+ err |= ra_fail(output, loc, Location(), "Definition %d not aligned correctly", i);
if (!assignments[def.tempId()].firstloc.block)
assignments[def.tempId()].firstloc = loc;
assignments[def.tempId()].defloc = loc;
PhysReg reg = assignments.at(tmp.id()).reg;
for (unsigned j = 0; j < tmp.bytes(); j++) {
if (regs[reg.reg_b + j])
- err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + i]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
+ err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
regs[reg.reg_b + j] = tmp.id();
}
+ if (def.regClass().is_subdword() && def.bytes() < 4) {
+ unsigned written = get_subdword_bytes_written(program, instr, i);
+ /* If written=4, the instruction still might write the upper half. In that case, it's the lower half that isn't preserved */
+ for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) {
+ unsigned written_reg = reg.reg() * 4u + j;
+ if (regs[written_reg] && regs[written_reg] != def.tempId())
+ err |= ra_fail(output, loc, assignments.at(regs[written_reg]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[written_reg]);
+ }
+ }
}
for (const Definition& def : instr->definitions) {
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