{"name": "RE_Z", "value": 2},
{"name": "EARLY_Z_THEN_RE_Z", "value": 3}
]
+ },
+ "ThreadTraceRegInclude": {
+ "entries": [
+ {"name": "REG_INCLUDE_SQDEC", "value": 1},
+ {"name": "REG_INCLUDE_SHDEC", "value": 2},
+ {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
+ {"name": "REG_INCLUDE_COMP", "value": 8},
+ {"name": "REG_INCLUDE_CONTEXT", "value": 16},
+ {"name": "REG_INCLUDE_CONFIG", "value": 32},
+ {"name": "REG_INCLUDE_OTHER", "value": 64},
+ {"name": "REG_INCLUDE_READS", "value": 128}
+ ]
+ },
+ "ThreadTraceTokenExclude": {
+ "entries": [
+ {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
+ {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
+ {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
+ {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
+ {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
+ {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
+ {"name": "TOKEN_EXCLUDE_REG", "value": 64},
+ {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
+ {"name": "TOKEN_EXCLUDE_INST", "value": 256},
+ {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
+ {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
+ {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
+ ]
}
},
"register_mappings": [
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36096, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_BUF0_BASE",
+ "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36100, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_BUF0_SIZE",
+ "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36112, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_WPTR",
+ "type_ref": "SQ_THREAD_TRACE_WPTR"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36116, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_MASK",
+ "type_ref": "SQ_THREAD_TRACE_MASK"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36120, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_TOKEN_MASK",
+ "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36124, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_CTRL",
+ "type_ref": "SQ_THREAD_TRACE_CTRL"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36128, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_STATUS",
+ "type_ref": "SQ_THREAD_TRACE_STATUS"
+ },
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 36132, "to": "mm"},
+ "name": "SQ_THREAD_TRACE_DROPPED_CNTR",
+ "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
+ },
{
"chips": ["gfx10"],
"map": {"at": 37804, "to": "mm"},
{
"chips": ["gfx10"],
"map": {"at": 47248, "to": "mm"},
- "name": "COMPUTE_PREF_PRI_ACCUM_0",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "COMPUTE_USER_ACCUM_0",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 47252, "to": "mm"},
- "name": "COMPUTE_PREF_PRI_ACCUM_1",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "COMPUTE_USER_ACCUM_1",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 47256, "to": "mm"},
- "name": "COMPUTE_PREF_PRI_ACCUM_2",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "COMPUTE_USER_ACCUM_2",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 47260, "to": "mm"},
- "name": "COMPUTE_PREF_PRI_ACCUM_3",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "COMPUTE_USER_ACCUM_3",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"name": "GE_USER_VGPR3",
"type_ref": "COMPUTE_PGM_LO"
},
+ {
+ "chips": ["gfx10"],
+ "map": {"at": 199048, "to": "mm"},
+ "name": "GE_USER_VGPR_EN",
+ "type_ref": "GE_USER_VGPR_EN"
+ },
{
"chips": ["gfx10"],
"map": {"at": 165840, "to": "mm"},
{
"chips": ["gfx10"],
"map": {"at": 45768, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_0",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45772, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_1",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45776, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_2",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45780, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_ESGS_3",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 46280, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_0",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 46284, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_1",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 46288, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_2",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 46292, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_LSHS_3",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45256, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_0",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_PS_0",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45260, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_1",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_PS_1",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45264, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_2",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_PS_2",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45268, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_PS_3",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_PS_3",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45512, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_0",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_VS_0",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45516, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_1",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_VS_1",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45520, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_2",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_VS_2",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
"map": {"at": 45524, "to": "mm"},
- "name": "SPI_SHADER_PREF_PRI_ACCUM_VS_3",
- "type_ref": "COMPUTE_PREF_PRI_ACCUM_0"
+ "name": "SPI_SHADER_USER_ACCUM_VS_3",
+ "type_ref": "COMPUTE_USER_ACCUM_0"
},
{
"chips": ["gfx10"],
{"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
]
},
- "COMPUTE_PREF_PRI_ACCUM_0": {
+ "COMPUTE_USER_ACCUM_0": {
"fields": [
- {"bits": [0, 2], "name": "COEFFICIENT_HIER_SELECT"},
- {"bits": [3, 5], "name": "CONTRIBUTION_HIER_SELECT"},
- {"bits": [6, 6], "name": "GROUP_UPDATE_EN"},
- {"bits": [7, 7], "name": "RESERVED"},
- {"bits": [8, 15], "name": "COEFFICIENT"},
- {"bits": [16, 23], "name": "CONTRIBUTION"}
+ {"bits": [0, 6], "name": "CONTRIBUTION"}
]
},
"COMPUTE_PREF_PRI_CNTR_CTRL": {
{"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
{"bits": [9, 17], "name": "VERT_GRP_SIZE"},
{"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
- {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"},
- {"bits": [21, 21], "name": "EN_USER_VGPR1"},
- {"bits": [22, 22], "name": "EN_USER_VGPR2"},
- {"bits": [23, 23], "name": "EN_USER_VGPR3"}
+ {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
+ ]
+ },
+ "GE_USER_VGPR_EN": {
+ "fields": [
+ {"bits": [0, 0], "name": "EN_USER_VGPR1"},
+ {"bits": [1, 1], "name": "EN_USER_VGPR2"},
+ {"bits": [2, 2], "name": "EN_USER_VGPR3"}
]
},
"GE_DMA_FIRST_INDEX": {
{"bits": [0, 0], "name": "FORCE_EN"}
]
},
+ "SQ_THREAD_TRACE_BUF0_BASE": {
+ "fields": [
+ {"bits": [0, 31], "name": "BASE_LO"}
+ ]
+ },
+ "SQ_THREAD_TRACE_BUF0_SIZE": {
+ "fields": [
+ {"bits": [0, 3], "name": "BASE_HI"},
+ {"bits": [8, 29], "name": "SIZE"}
+ ]
+ },
+ "SQ_THREAD_TRACE_WPTR": {
+ "fields": [
+ {"bits": [0, 28], "name": "OFFSET"},
+ {"bits": [31, 31], "name": "BUFFER_ID"}
+ ]
+ },
+ "SQ_THREAD_TRACE_MASK": {
+ "fields": [
+ {"bits": [0, 1], "name": "SIMD_SEL"},
+ {"bits": [4, 7], "name": "WGP_SEL"},
+ {"bits": [9, 9], "name": "SA_SEL"},
+ {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
+ ]
+ },
+ "SQ_THREAD_TRACE_TOKEN_MASK": {
+ "fields": [
+ {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
+ {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
+ {"bits": [24, 25], "name": "INST_EXCLUDE"},
+ {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
+ ]
+ },
+ "SQ_THREAD_TRACE_CTRL": {
+ "fields": [
+ {"bits": [0, 1], "name": "MODE"},
+ {"bits": [2, 2], "name": "ALL_VMID"},
+ {"bits": [3, 3], "name": "CH_PERF_END"},
+ {"bits": [4, 4], "name": "INTERRUPT_EN"},
+ {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
+ {"bits": [6, 8], "name": "HIWATER"},
+ {"bits": [9, 9], "name": "REG_STALL_EN"},
+ {"bits": [10, 10], "name": "SPI_STALL_EN"},
+ {"bits": [11, 11], "name": "SQ_STALL_EN"},
+ {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
+ {"bits": [13, 13], "name": "UTIL_TIMER"},
+ {"bits": [14, 15], "name": "WAVESTART_MODE"},
+ {"bits": [16, 17], "name": "RT_FREQ"},
+ {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
+ {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
+ {"bits": [30, 30], "name": "CAPTURE_ALL"},
+ {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
+ ]
+ },
+ "SQ_THREAD_TRACE_STATUS": {
+ "fields": [
+ {"bits": [0, 11], "name": "FINISH_PENDING"},
+ {"bits": [12, 23], "name": "FINISH_DONE"},
+ {"bits": [24, 24], "name": "UTC_ERR"},
+ {"bits": [25, 25], "name": "BUSY"},
+ {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
+ {"bits": [27, 27], "name": "EVENT_CNTR_STALL"}
+ ]
+ },
+ "SQ_THREAD_TRACE_DROPPED_CNTR": {
+ "fields": [
+ {"bits": [0, 31], "name": "CNTR"}
+ ]
+ },
"SX_BLEND_OPT_CONTROL": {
"fields": [
{"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
projects / mesa.git / blobdiff