radv: add set_loc_shader_ptr() helper

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index baab8db6170a7a04a99e4de5594469fce7487cdc..3636b2c8d9c075be66a217bee68e2e30ef742a39 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -238,7 +238,7 @@ static VkResult radv_create_cmd_buffer(
                cmd_buffer->queue_family_index = pool->queue_family_index;
 
        } else {
-               /* Init the pool_link so we can safefly call list_del when we destroy
+               /* Init the pool_link so we can safely call list_del when we destroy
                 * the command buffer
                 */
                list_inithead(&cmd_buffer->pool_link);
@@ -347,7 +347,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
                                       new_size, 4096,
                                       RADEON_DOMAIN_GTT,
                                       RADEON_FLAG_CPU_ACCESS|
-                                      RADEON_FLAG_NO_INTERPROCESS_SHARING);
+                                      RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                                      RADEON_FLAG_32BIT);
 
        if (!bo) {
                cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
@@ -587,9 +588,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
                return;
        assert(loc->num_sgprs == 2);
        assert(!loc->indirect);
-       radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-       radeon_emit(cmd_buffer->cs, va);
-       radeon_emit(cmd_buffer->cs, va >> 32);
+
+       radv_emit_shader_pointer(cmd_buffer->cs,
+                                base_reg + loc->sgpr_idx * 4, va);
 }
 
 static void
@@ -1156,7 +1157,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 }
 
 /*
- *with DCC some colors don't require CMASK elimiation before being
+ * With DCC some colors don't require CMASK elimination before being
  * used as a texture. This sets a predicate value to determine if the
  * cmask eliminate is required.
  */
@@ -1334,6 +1335,7 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
 
 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
 {
+       bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
        struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
        uint32_t pa_sc_mode_cntl_1 =
                pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
@@ -1342,11 +1344,12 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
        if(!cmd_buffer->state.active_occlusion_queries) {
                if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
                        if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
-                           pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
+                           pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
+                           has_perfect_queries) {
                                /* Re-enable out-of-order rasterization if the
                                 * bound pipeline supports it and if it's has
-                                * been disabled before starting occlusion
-                                * queries.
+                                * been disabled before starting any perfect
+                                * occlusion queries.
                                 */
                                radeon_set_context_reg(cmd_buffer->cs,
                                                       R_028A4C_PA_SC_MODE_CNTL_1,
@@ -1359,22 +1362,22 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
        } else {
                const struct radv_subpass *subpass = cmd_buffer->state.subpass;
                uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
-               bool perfect = cmd_buffer->state.perfect_occlusion_queries_enabled;
 
                if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
                        db_count_control =
-                               S_028004_PERFECT_ZPASS_COUNTS(perfect) |
+                               S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
                                S_028004_SAMPLE_RATE(sample_rate) |
                                S_028004_ZPASS_ENABLE(1) |
                                S_028004_SLICE_EVEN_ENABLE(1) |
                                S_028004_SLICE_ODD_ENABLE(1);
 
                        if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
-                           pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
+                           pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
+                           has_perfect_queries) {
                                /* If the bound pipeline has enabled
                                 * out-of-order rasterization, we should
-                                * disable it before starting occlusion
-                                * queries.
+                                * disable it before starting any perfect
+                                * occlusion queries.
                                 */
                                pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
 
@@ -1440,10 +1443,9 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
 
        assert(!desc_set_loc->indirect);
        assert(desc_set_loc->num_sgprs == 2);
-       radeon_set_sh_reg_seq(cmd_buffer->cs,
-                             base_reg + desc_set_loc->sgpr_idx * 4, 2);
-       radeon_emit(cmd_buffer->cs, va);
-       radeon_emit(cmd_buffer->cs, va >> 32);
+
+       radv_emit_shader_pointer(cmd_buffer->cs,
+                                base_reg + desc_set_loc->sgpr_idx * 4, va);
 }
 
 static void