freedreno: re-work fd_batch_reference() locking

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 41435d0649e28fc80966870f9c41994d31f532de..3646c1ae89e3bff9676a494d5650ed0c0cafea78 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -528,10 +528,8 @@ void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
                radv_get_descriptors_state(cmd_buffer, bind_point);
 
        descriptors_state->sets[idx] = set;
-       if (set)
-               descriptors_state->valid |= (1u << idx);
-       else
-               descriptors_state->valid &= ~(1u << idx);
+
+       descriptors_state->valid |= (1u << idx); /* active descriptors */
        descriptors_state->dirty |= (1u << idx);
 }
 
@@ -1968,8 +1966,15 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
                      VkAccessFlags src_flags,
                      struct radv_image *image)
 {
+       bool flush_CB_meta = true, flush_DB_meta = true;
        enum radv_cmd_flush_bits flush_bits = 0;
        uint32_t b;
+
+       if (image && !radv_image_has_CB_metadata(image))
+               flush_CB_meta = false;
+       if (image && !radv_image_has_htile(image))
+               flush_DB_meta = false;
+
        for_each_bit(b, src_flags) {
                switch ((VkAccessFlagBits)(1 << b)) {
                case VK_ACCESS_SHADER_WRITE_BIT:
@@ -1977,22 +1982,23 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
                        break;
                case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
                        flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
-                       if (!image || (image && radv_image_has_CB_metadata(image))) {
+                       if (flush_CB_meta)
                                flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
-                       }
                        break;
                case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
                        flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
-                       if (!image || (image && radv_image_has_htile(image))) {
+                       if (flush_DB_meta)
                                flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
-                       }
                        break;
                case VK_ACCESS_TRANSFER_WRITE_BIT:
                        flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
-                                     RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
                                      RADV_CMD_FLAG_FLUSH_AND_INV_DB |
-                                     RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
                                      RADV_CMD_FLAG_INV_GLOBAL_L2;
+
+                       if (flush_CB_meta)
+                               flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+                       if (flush_DB_meta)
+                               flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
                        break;
                default:
                        break;
@@ -2401,9 +2407,8 @@ radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
        struct radeon_winsys *ws = cmd_buffer->device->ws;
 
        radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
-       if (!set)
-               return;
 
+       assert(set);
        assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
 
        if (!cmd_buffer->device->use_global_bo_list) {