radv: add radv_dump_pipeline_state() helper

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index baa28d408becee3a4f6bc8b30b8317a61d35af8a..5ab577b4c5911d387f6b0fe0185f55218cba8064 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -238,7 +238,7 @@ static VkResult radv_create_cmd_buffer(
                cmd_buffer->queue_family_index = pool->queue_family_index;
 
        } else {
-               /* Init the pool_link so we can safefly call list_del when we destroy
+               /* Init the pool_link so we can safely call list_del when we destroy
                 * the command buffer
                 */
                list_inithead(&cmd_buffer->pool_link);
@@ -347,7 +347,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
                                       new_size, 4096,
                                       RADEON_DOMAIN_GTT,
                                       RADEON_FLAG_CPU_ACCESS|
-                                      RADEON_FLAG_NO_INTERPROCESS_SHARING);
+                                      RADEON_FLAG_NO_INTERPROCESS_SHARING |
+                                      RADEON_FLAG_32BIT);
 
        if (!bo) {
                cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
@@ -585,11 +586,12 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
        uint32_t base_reg = pipeline->user_data_0[stage];
        if (loc->sgpr_idx == -1)
                return;
-       assert(loc->num_sgprs == 2);
+
+       assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
        assert(!loc->indirect);
-       radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-       radeon_emit(cmd_buffer->cs, va);
-       radeon_emit(cmd_buffer->cs, va >> 32);
+
+       radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
+                                base_reg + loc->sgpr_idx * 4, va, false);
 }
 
 static void
@@ -1156,7 +1158,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 }
 
 /*
- *with DCC some colors don't require CMASK elimiation before being
+ * With DCC some colors don't require CMASK elimination before being
  * used as a texture. This sets a predicate value to determine if the
  * cmask eliminate is required.
  */
@@ -1441,11 +1443,10 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
                return;
 
        assert(!desc_set_loc->indirect);
-       assert(desc_set_loc->num_sgprs == 2);
-       radeon_set_sh_reg_seq(cmd_buffer->cs,
-                             base_reg + desc_set_loc->sgpr_idx * 4, 2);
-       radeon_emit(cmd_buffer->cs, va);
-       radeon_emit(cmd_buffer->cs, va >> 32);
+       assert(desc_set_loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
+
+       radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
+                                base_reg + desc_set_loc->sgpr_idx * 4, va, false);
 }
 
 static void