if (mask & RADV_PREFETCH_GS) {
radv_emit_shader_prefetch(cmd_buffer,
pipeline->shaders[MESA_SHADER_GEOMETRY]);
- radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
+ if (pipeline->gs_copy_shader)
+ radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
}
if (mask & RADV_PREFETCH_PS)
pipeline->shaders[i]->bo);
}
- if (radv_pipeline_has_gs(pipeline))
+ if (radv_pipeline_has_gs(pipeline) && pipeline->gs_copy_shader)
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
pipeline->gs_copy_shader->bo);
radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
int index,
struct radv_attachment_info *att,
- struct radv_image *image,
+ struct radv_image_view *iview,
VkImageLayout layout)
{
bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
struct radv_color_buffer_info *cb = &att->cb;
uint32_t cb_color_info = cb->cb_color_info;
+ struct radv_image *image = iview->image;
if (!radv_layout_dcc_compressed(image, layout,
radv_image_queue_family_mask(image,
cb_color_info &= C_028C70_DCC_ENABLE;
}
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ if (radv_image_is_tc_compat_cmask(image) &&
+ (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
+ radv_is_dcc_decompress_pipeline(cmd_buffer))) {
+ /* If this bit is set, the FMASK decompression operation
+ * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
+ */
+ cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
+ }
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
+ radeon_emit(cmd_buffer->cs, cb->cb_color_base);
+ radeon_emit(cmd_buffer->cs, 0);
+ radeon_emit(cmd_buffer->cs, 0);
+ radeon_emit(cmd_buffer->cs, cb->cb_color_view);
+ radeon_emit(cmd_buffer->cs, cb_color_info);
+ radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
+ radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
+ radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
+ radeon_emit(cmd_buffer->cs, 0);
+ radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
+ radeon_emit(cmd_buffer->cs, 0);
+
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 1);
+ radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
+
+ radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,
+ cb->cb_color_base >> 32);
+ radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,
+ cb->cb_color_cmask >> 32);
+ radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,
+ cb->cb_color_fmask >> 32);
+ radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,
+ cb->cb_dcc_base >> 32);
+ radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,
+ cb->cb_color_attrib2);
+ radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
+ cb->cb_color_attrib3);
+ } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
}
}
- if (radv_image_has_dcc(image)) {
+ if (radv_dcc_enabled(image, iview->base_mip)) {
/* Drawing with DCC enabled also compresses colorbuffers. */
- radv_update_dcc_metadata(cmd_buffer, image, true);
+ VkImageSubresourceRange range = {
+ .aspectMask = iview->aspect_mask,
+ .baseMipLevel = iview->base_mip,
+ .levelCount = iview->level_count,
+ .baseArrayLayer = iview->base_layer,
+ .layerCount = iview->layer_count,
+ };
+
+ radv_update_dcc_metadata(cmd_buffer, image, &range, true);
}
}
db_z_info &= C_028040_ZRANGE_PRECISION;
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
db_z_info_reg = R_028038_DB_Z_INFO;
} else {
db_z_info_reg = R_028040_DB_Z_INFO;
radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
-
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
+ radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
+
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);
+ radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));
+ radeon_emit(cmd_buffer->cs, db_z_info);
+ radeon_emit(cmd_buffer->cs, db_stencil_info);
+ radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
+ radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
+ radeon_emit(cmd_buffer->cs, ds->db_z_read_base);
+ radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);
+
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);
+ radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
+ radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
+ radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
+ radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
+ radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
+ } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
struct radv_image *image,
VkClearDepthStencilValue ds_clear_value)
{
- uint64_t va = radv_buffer_get_va(image->bo);
- va += image->offset + image->tc_compat_zrange_offset;
uint32_t cond_val;
/* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
*/
void
radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, bool value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, bool value)
{
uint64_t pred_val = value;
- uint64_t va = radv_buffer_get_va(image->bo);
- va += image->offset + image->fce_pred_offset;
+ uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
+ uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t count = 2 * level_count;
- assert(radv_image_has_dcc(image));
+ assert(radv_dcc_enabled(image, range->baseMipLevel));
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
- radeon_emit(cmd_buffer->cs, pred_val);
- radeon_emit(cmd_buffer->cs, pred_val >> 32);
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ radeon_emit(cmd_buffer->cs, pred_val);
+ radeon_emit(cmd_buffer->cs, pred_val >> 32);
+ }
}
/**
*/
void
radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, bool value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, bool value)
{
uint64_t pred_val = value;
- uint64_t va = radv_buffer_get_va(image->bo);
- va += image->offset + image->dcc_pred_offset;
+ uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
+ uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t count = 2 * level_count;
- assert(radv_image_has_dcc(image));
+ assert(radv_dcc_enabled(image, range->baseMipLevel));
- radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
+ radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
- radeon_emit(cmd_buffer->cs, pred_val);
- radeon_emit(cmd_buffer->cs, pred_val >> 32);
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ radeon_emit(cmd_buffer->cs, pred_val);
+ radeon_emit(cmd_buffer->cs, pred_val >> 32);
+ }
}
/**
uint32_t level_count = radv_get_levelCount(image, range);
uint32_t count = 2 * level_count;
- assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
+ assert(radv_image_has_cmask(image) ||
+ radv_dcc_enabled(image, range->baseMipLevel));
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
.layerCount = iview->layer_count,
};
- assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
+ assert(radv_image_has_cmask(image) ||
+ radv_dcc_enabled(image, iview->base_mip));
radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);
*/
static void
radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image,
+ struct radv_image_view *iview,
int cb_idx)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
- uint64_t va = radv_buffer_get_va(image->bo);
-
- va += image->offset + image->clear_value_offset;
+ struct radv_image *image = iview->image;
+ uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
- if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
+ if (!radv_image_has_cmask(image) &&
+ !radv_dcc_enabled(image, iview->base_mip))
return;
uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
int i;
struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
- unsigned num_bpp64_colorbufs = 0;
/* this may happen for inherited secondary recording */
if (!framebuffer)
int idx = subpass->color_attachments[i].attachment;
struct radv_attachment_info *att = &framebuffer->attachments[idx];
- struct radv_image *image = att->attachment->image;
+ struct radv_image_view *iview = att->attachment;
VkImageLayout layout = subpass->color_attachments[i].layout;
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
assert(att->attachment->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
- radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
-
- radv_load_color_clear_metadata(cmd_buffer, image, i);
+ radv_emit_fb_color_state(cmd_buffer, i, att, iview, layout);
- if (image->planes[0].surface.bpe >= 8)
- num_bpp64_colorbufs++;
+ radv_load_color_clear_metadata(cmd_buffer, iview, i);
}
if (subpass->depth_stencil_attachment) {
}
radv_load_ds_clear_metadata(cmd_buffer, image);
} else {
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)
radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
else
radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
S_028208_BR_Y(framebuffer->height));
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
- uint8_t watermark = 4; /* Default value for GFX8. */
-
- /* For optimal DCC performance. */
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
- if (num_bpp64_colorbufs >= 5) {
- watermark = 8;
- } else {
- watermark = 6;
- }
- }
+ bool disable_constant_encode =
+ cmd_buffer->device->physical_device->has_dcc_constant_encode;
+ enum chip_class chip_class =
+ cmd_buffer->device->physical_device->rad_info.chip_class;
+ uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
- S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
- S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
+ S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
+ S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
+ S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
}
if (cmd_buffer->device->dfsm_allowed) {
if (state->index_type != state->last_index_type) {
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
- radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
+ radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
+ cs, R_03090C_VGT_INDEX_TYPE,
2, state->index_type);
} else {
radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
- S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
+ S_008F0C_OOB_SELECT(1) |
+ S_008F0C_RESOURCE_LEVEL(1);
+ } else {
+ desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ }
}
va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
};
static void
-radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
- const struct radv_draw_info *draw_info)
+si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
+ bool instanced_draw, bool indirect_draw,
+ bool count_from_stream_output,
+ uint32_t draw_vertex_count)
{
struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
- uint32_t ia_multi_vgt_param;
- int32_t primitive_reset_en;
+ unsigned ia_multi_vgt_param;
- /* Draw state. */
ia_multi_vgt_param =
- si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
- draw_info->indirect,
- !!draw_info->strmout_buffer,
- draw_info->indirect ? 0 : draw_info->count);
+ si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
+ indirect_draw,
+ count_from_stream_output,
+ draw_vertex_count);
if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
if (info->chip_class >= GFX9) {
- radeon_set_uconfig_reg_idx(cs,
+ radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
+ cs,
R_030960_IA_MULTI_VGT_PARAM,
4, ia_multi_vgt_param);
} else if (info->chip_class >= GFX7) {
}
state->last_ia_multi_vgt_param = ia_multi_vgt_param;
}
+}
+
+static void
+radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
+ const struct radv_draw_info *draw_info)
+{
+ struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
+ struct radv_cmd_state *state = &cmd_buffer->state;
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
+ int32_t primitive_reset_en;
+
+ /* Draw state. */
+ if (info->chip_class < GFX10) {
+ si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
+ draw_info->indirect,
+ !!draw_info->strmout_buffer,
+ draw_info->indirect ? 0 : draw_info->count);
+ }
/* Primitive restart. */
primitive_reset_en =
case VK_ACCESS_SHADER_WRITE_BIT:
case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
- flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ flush_bits |= RADV_CMD_FLAG_WB_L2;
break;
case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
case VK_ACCESS_TRANSFER_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_DB |
- RADV_CMD_FLAG_INV_GLOBAL_L2;
+ RADV_CMD_FLAG_INV_L2;
if (flush_CB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
if (!radv_image_has_htile(image))
flush_DB_meta = false;
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* TODO: implement shader coherent for GFX10 */
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
if (image->info.samples == 1 &&
(image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
break;
case VK_ACCESS_UNIFORM_READ_BIT:
- flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
+ flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
break;
case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
case VK_ACCESS_TRANSFER_READ_BIT:
case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
- flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
- RADV_CMD_FLAG_INV_GLOBAL_L2;
+ flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
+ RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_SHADER_READ_BIT:
- flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
+ flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
if (!image_is_coherent)
- flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
+ flush_bits |= RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
if (flush_CB)
NULL);
}
-static uint32_t
+uint32_t
radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_cmd_state *state = &cmd_buffer->state;
dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
- S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ dst[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+ S_008F0C_OOB_SELECT(3) |
+ S_008F0C_RESOURCE_LEVEL(1);
+ } else {
+ dst[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ }
+
cmd_buffer->push_constant_stages |=
set->layout->dynamic_shader_stages;
}
if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
- cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
/* Make sure to sync all pending active queries at the end of
* command buffer.
if (secondary->sample_positions_needed)
primary->sample_positions_needed = true;
+ if (!secondary->state.framebuffer &&
+ (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
+ /* Emit the framebuffer state from primary if secondary
+ * has been recorded without a framebuffer, otherwise
+ * fast color/depth clears can't work.
+ */
+ radv_emit_framebuffer_state(primary);
+ }
+
primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
}
static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range,
+ uint32_t value)
{
struct radv_cmd_state *state = &cmd_buffer->state;
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
+ state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range)
{
struct radv_cmd_state *state = &cmd_buffer->state;
static const uint32_t fmask_clear_values[4] = {
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
+ state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
{
struct radv_cmd_state *state = &cmd_buffer->state;
+ unsigned size = 0;
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
+ state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
+ /* When DCC is enabled with mipmaps, some levels might not
+ * support fast clears and we have to initialize them as "fully
+ * expanded".
+ */
+ /* Compute the size of all fast clearable DCC levels. */
+ for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
+ struct legacy_surf_level *surf_level =
+ &image->planes[0].surface.u.legacy.level[i];
+ unsigned dcc_fast_clear_size =
+ surf_level->dcc_slice_fast_clear_size * image->info.array_size;
+
+ if (!dcc_fast_clear_size)
+ break;
+
+ size = surf_level->dcc_offset + dcc_fast_clear_size;
+ }
+
+ /* Initialize the mipmap levels without DCC. */
+ if (size != image->planes[0].surface.dcc_size) {
+ state->flush_bits |=
+ radv_fill_buffer(cmd_buffer, image->bo,
+ image->offset + image->dcc_offset + size,
+ image->planes[0].surface.dcc_size - size,
+ 0xffffffff);
+ }
+ }
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
value = 0xccccccccu;
}
- radv_initialise_cmask(cmd_buffer, image, value);
+ radv_initialise_cmask(cmd_buffer, image, range, value);
}
if (radv_image_has_fmask(image)) {
- radv_initialize_fmask(cmd_buffer, image);
+ radv_initialize_fmask(cmd_buffer, image, range);
}
- if (radv_image_has_dcc(image)) {
+ if (radv_dcc_enabled(image, range->baseMipLevel)) {
uint32_t value = 0xffffffffu; /* Fully expanded mode. */
bool need_decompress_pass = false;
need_decompress_pass = true;
}
- radv_initialize_dcc(cmd_buffer, image, value);
+ radv_initialize_dcc(cmd_buffer, image, range, value);
- radv_update_fce_metadata(cmd_buffer, image,
+ radv_update_fce_metadata(cmd_buffer, image, range,
need_decompress_pass);
}
- if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
+ if (radv_image_has_cmask(image) ||
+ radv_dcc_enabled(image, range->baseMipLevel)) {
uint32_t color_values[2] = {};
radv_set_color_clear_metadata(cmd_buffer, image, range,
color_values);
return;
}
- if (radv_image_has_dcc(image)) {
+ if (radv_dcc_enabled(image, range->baseMipLevel)) {
if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
- radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
+ radv_initialize_dcc(cmd_buffer, image, range, 0xffffffffu);
} else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
!radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
radv_decompress_dcc(cmd_buffer, image, range);
assert(src_family == cmd_buffer->queue_family_index ||
dst_family == cmd_buffer->queue_family_index);
- if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
+ if (src_family == VK_QUEUE_FAMILY_EXTERNAL ||
+ src_family == VK_QUEUE_FAMILY_FOREIGN_EXT)
return;
if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
radv_draw(cmd_buffer, &info);
}
+
+/* VK_AMD_buffer_marker */
+void radv_CmdWriteBufferMarkerAMD(
+ VkCommandBuffer commandBuffer,
+ VkPipelineStageFlagBits pipelineStage,
+ VkBuffer dstBuffer,
+ VkDeviceSize dstOffset,
+ uint32_t marker)
+{
+ RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
+ RADV_FROM_HANDLE(radv_buffer, buffer, dstBuffer);
+ struct radeon_cmdbuf *cs = cmd_buffer->cs;
+ uint64_t va = radv_buffer_get_va(buffer->bo) + dstOffset;
+
+ si_emit_cache_flush(cmd_buffer);
+
+ if (!(pipelineStage & ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
+ radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+ radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
+ COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
+ COPY_DATA_WR_CONFIRM);
+ radeon_emit(cs, marker);
+ radeon_emit(cs, 0);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ } else {
+ si_cs_emit_write_event_eop(cs,
+ cmd_buffer->device->physical_device->rad_info.chip_class,
+ radv_cmd_buffer_uses_mec(cmd_buffer),
+ V_028A90_BOTTOM_OF_PIPE_TS, 0,
+ EOP_DATA_SEL_VALUE_32BIT,
+ va, marker,
+ cmd_buffer->gfx9_eop_bug_va);
+ }
+}
projects / mesa.git / blobdiff