radv: set some dcc parameters depending on if texture will be sampled

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d6aaff707b557e95863d27a61ce23aa2a27b2566..6a89d4e568d96219b844faadc6eee16c57be682d 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -593,7 +593,8 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
        radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
        radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
 
-       if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
+       if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
+           old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
                return;
 
        radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
@@ -1753,7 +1754,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
        uint64_t va;
 
        stages &= cmd_buffer->push_constant_stages;
-       if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
+       if (!stages ||
+           (!layout->push_constant_size && !layout->dynamic_offset_count))
                return;
 
        if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
@@ -2561,6 +2563,7 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
 {
        struct radv_shader_variant *compute_shader;
        struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
+       struct radv_device *device = cmd_buffer->device;
        unsigned compute_resource_limits;
        unsigned waves_per_threadgroup;
        uint64_t va;
@@ -2602,6 +2605,19 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
        compute_resource_limits =
                S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
 
+       if (device->physical_device->rad_info.chip_class >= CIK) {
+               unsigned num_cu_per_se =
+                       device->physical_device->rad_info.num_good_compute_units /
+                       device->physical_device->rad_info.max_se;
+
+               /* Force even distribution on all SIMDs in CU if the workgroup
+                * size is 64. This has shown some good improvements if # of
+                * CUs per SE is not a multiple of 4.
+                */
+               if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
+                       compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
+       }
+
        radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
                          compute_resource_limits);