radv: only allocate the GFX9 fence and EOP BOs for the gfx queue

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c8d1fc265d75aaa8bd4890e8e5045c8a2ca2cf2d..a260596c711a2386bcd5ae176e2087db22b3dd15 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -332,7 +332,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
                cmd_buffer->descriptors[i].push_dirty = false;
        }
 
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
+           cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
                unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
                unsigned eop_bug_offset;
                void *fence_ptr;