radv: emit framebuffer state from primary if secondary doesn't inherit it

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a26bf6c6a6701354512abde9ddb322871e36a91a..bf2ecc4b0b46b934e2a2de7f763f955789d38acd 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1255,6 +1255,15 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
                cb_color_info &= C_028C70_DCC_ENABLE;
        }
 
+       if (radv_image_is_tc_compat_cmask(image) &&
+           (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
+            radv_is_dcc_decompress_pipeline(cmd_buffer))) {
+               /* If this bit is set, the FMASK decompression operation
+                * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
+                */
+               cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
+       }
+
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
                radeon_emit(cmd_buffer->cs, cb->cb_color_base);
@@ -3715,6 +3724,15 @@ void radv_CmdExecuteCommands(
                if (secondary->sample_positions_needed)
                        primary->sample_positions_needed = true;
 
+               if (!secondary->state.framebuffer &&
+                   (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
+                       /* Emit the framebuffer state from primary if secondary
+                        * has been recorded without a framebuffer, otherwise
+                        * fast color/depth clears can't work.
+                        */
+                       radv_emit_framebuffer_state(primary);
+               }
+
                primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
 
 
@@ -4912,11 +4930,58 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
                         const VkImageSubresourceRange *range, uint32_t value)
 {
        struct radv_cmd_state *state = &cmd_buffer->state;
+       uint32_t level_count = radv_get_levelCount(image, range);
+       unsigned size = 0;
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 
-       state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+               /* Mipmap level aren't implemented. */
+               assert(level_count == 1);
+               state->flush_bits |= radv_clear_dcc(cmd_buffer, image,
+                                                   range, value);
+       } else {
+               /* Initialize the mipmap levels with DCC first. */
+               for (unsigned l = 0; l < level_count; l++) {
+                       uint32_t level = range->baseMipLevel + l;
+                       struct legacy_surf_level *surf_level =
+                               &image->planes[0].surface.u.legacy.level[level];
+
+                       if (!surf_level->dcc_fast_clear_size)
+                               break;
+
+                       state->flush_bits |=
+                               radv_dcc_clear_level(cmd_buffer, image,
+                                                    level, value);
+               }
+
+               /* When DCC is enabled with mipmaps, some levels might not
+                * support fast clears and we have to initialize them as "fully
+                * expanded".
+                */
+               if (image->planes[0].surface.num_dcc_levels > 1) {
+                       /* Compute the size of all fast clearable DCC levels. */
+                       for (unsigned i = 0; i < image->planes[0].surface.num_dcc_levels; i++) {
+                               struct legacy_surf_level *surf_level =
+                                       &image->planes[0].surface.u.legacy.level[i];
+
+                               if (!surf_level->dcc_fast_clear_size)
+                                       break;
+
+                               size = surf_level->dcc_offset + surf_level->dcc_fast_clear_size;
+                       }
+
+                       /* Initialize the mipmap levels without DCC. */
+                       if (size != image->planes[0].surface.dcc_size) {
+                               state->flush_bits |=
+                                       radv_fill_buffer(cmd_buffer, image->bo,
+                                                        image->offset + image->dcc_offset + size,
+                                                        image->planes[0].surface.dcc_size - size,
+                                                        0xffffffff);
+                       }
+               }
+       }
 
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;