radv: only flush DB meta in pipeline image barriers when needed

[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 50f4aad0ec1bd9af56ba02a3c852196236f30950..da6748edff2774627be9a4563463899a809af601 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1967,7 +1967,8 @@ static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
 
 static enum radv_cmd_flush_bits
 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
-                                 VkAccessFlags src_flags)
+                     VkAccessFlags src_flags,
+                     struct radv_image *image)
 {
        enum radv_cmd_flush_bits flush_bits = 0;
        uint32_t b;
@@ -1981,8 +1982,10 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
                                      RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
                        break;
                case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
-                       flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
-                                     RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+                       flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
+                       if (!image || (image && radv_image_has_htile(image))) {
+                               flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+                       }
                        break;
                case VK_ACCESS_TRANSFER_WRITE_BIT:
                        flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
@@ -2041,7 +2044,8 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
 
 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
 {
-       cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
+       cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
+                                                             NULL);
        radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
        cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
                                                              NULL);
@@ -4203,20 +4207,24 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
        }
 
        for (uint32_t i = 0; i < memoryBarrierCount; i++) {
-               src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
+               src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
+                                                       NULL);
                dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
                                                        NULL);
        }
 
        for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
-               src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
+               src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
+                                                       NULL);
                dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
                                                        NULL);
        }
 
        for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
                RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
-               src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
+
+               src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
+                                                       image);
                dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
                                                        image);
        }