radv: tidy up radv_get_shader_name() and add NGG stages

[mesa.git] / src / amd / vulkan / radv_cs.h

diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 840597686a83706bef92a4901596f2152c8edbda..5f8b59c34cb173d3ac167f3d8fcadfe5e773de66 100644 (file)
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -28,10 +28,11 @@
 #include <string.h>
 #include <stdint.h>
 #include <assert.h>
+#include "radv_private.h"
 #include "sid.h"
 
 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
-                                      struct radeon_winsys_cs *cs,
+                                      struct radeon_cmdbuf *cs,
                                       unsigned needed)
 {
         if (cs->max_dw - cs->cdw < needed)
@@ -39,7 +40,7 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
         return cs->cdw + needed;
 }
 
-static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
         assert(reg < SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -48,13 +49,13 @@ static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsign
         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
         radeon_set_config_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
-static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
         assert(reg >= SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -63,14 +64,14 @@ static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsig
         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
         radeon_set_context_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
 
-static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
                                              unsigned reg, unsigned idx,
                                              unsigned value)
 {
@@ -81,7 +82,7 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
        radeon_emit(cs, value);
 }
 
-static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
        assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -90,13 +91,13 @@ static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned r
        radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
        radeon_set_sh_reg_seq(cs, reg, 1);
        radeon_emit(cs, value);
 }
 
-static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
        assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -105,19 +106,27 @@ static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsig
        radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
        radeon_set_uconfig_reg_seq(cs, reg, 1);
        radeon_emit(cs, value);
 }
 
-static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice,
+                                             struct radeon_cmdbuf *cs,
                                              unsigned reg, unsigned idx,
                                              unsigned value)
 {
        assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
        assert(cs->cdw + 3 <= cs->max_dw);
-       radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
+       assert(idx);
+
+       unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
+       if (pdevice->rad_info.chip_class < GFX9 ||
+           (pdevice->rad_info.chip_class == GFX9 && pdevice->rad_info.me_fw_version < 26))
+               opcode = PKT3_SET_UCONFIG_REG;
+
+       radeon_emit(cs, PKT3(opcode, 1, 0));
        radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
        radeon_emit(cs, value);
 }