ac,radv: remove the vec3 restriction with LLVM 9+

[mesa.git] / src / amd / vulkan / radv_cs.h

diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 6481df1357cdd995a39a71ac4799d9414bab9d4f..a5792fcc9590aeea8b09ff2f80c46dc4a5f636d6 100644 (file)
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -21,15 +21,17 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
-#pragma once
+
+#ifndef RADV_CS_H
+#define RADV_CS_H
 
 #include <string.h>
 #include <stdint.h>
 #include <assert.h>
-#include "r600d_common.h"
+#include "sid.h"
 
 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
-                                      struct radeon_winsys_cs *cs,
+                                      struct radeon_cmdbuf *cs,
                                       unsigned needed)
 {
         if (cs->max_dw - cs->cdw < needed)
@@ -37,75 +39,79 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
         return cs->cdw + needed;
 }
 
-static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
-        assert(reg < R600_CONTEXT_REG_OFFSET);
+        assert(reg < SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
+        assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
-        radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
+        radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
         radeon_set_config_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
-static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
-        assert(reg >= R600_CONTEXT_REG_OFFSET);
+        assert(reg >= SI_CONTEXT_REG_OFFSET);
         assert(cs->cdw + 2 + num <= cs->max_dw);
+        assert(num);
         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
-        radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
+        radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
         radeon_set_context_reg_seq(cs, reg, 1);
         radeon_emit(cs, value);
 }
 
 
-static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
                                              unsigned reg, unsigned idx,
                                              unsigned value)
 {
-       assert(reg >= R600_CONTEXT_REG_OFFSET);
+       assert(reg >= SI_CONTEXT_REG_OFFSET);
        assert(cs->cdw + 3 <= cs->max_dw);
        radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
-       radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
+       radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
        radeon_emit(cs, value);
 }
 
-static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
        assert(cs->cdw + 2 + num <= cs->max_dw);
+       assert(num);
        radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
        radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
        radeon_set_sh_reg_seq(cs, reg, 1);
        radeon_emit(cs, value);
 }
 
-static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
        assert(cs->cdw + 2 + num <= cs->max_dw);
+       assert(num);
        radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
        radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 }
 
-static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 {
        radeon_set_uconfig_reg_seq(cs, reg, 1);
        radeon_emit(cs, value);
 }
 
-static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
                                              unsigned reg, unsigned idx,
                                              unsigned value)
 {
@@ -115,3 +121,5 @@ static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
        radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
        radeon_emit(cs, value);
 }
+
+#endif /* RADV_CS_H */