#include <stdio.h>
#include <sys/utsname.h>
+#include "util/mesa-sha1.h"
#include "sid.h"
-#include "gfx9d.h"
#include "ac_debug.h"
#include "radv_debug.h"
#include "radv_shader.h"
device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
RADEON_DOMAIN_VRAM,
RADEON_FLAG_CPU_ACCESS|
- RADEON_FLAG_NO_INTERPROCESS_SHARING);
+ RADEON_FLAG_NO_INTERPROCESS_SHARING,
+ RADV_BO_PRIORITY_UPLOAD_BUFFER);
if (!device->trace_bo)
return false;
}
static void
-radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
+radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
{
const char *filename = getenv("RADV_TRACE_FILE");
FILE *f = fopen(filename, "w");
{
struct radeon_info *info = &device->physical_device->rad_info;
- if (info->drm_major == 2 && info->drm_minor < 42)
- return; /* no radeon support */
-
fprintf(f, "Memory-mapped registers:\n");
radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
- if (info->drm_major < 3 || info->drm_minor < 1) {
+ if (info->drm_minor < 1) {
fprintf(f, "\n");
return;
}
radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
- if (info->chip_class <= VI) {
+ if (info->chip_class <= GFX8) {
radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
FILE *f)
{
+ unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0
+ : R_008F10_SQ_IMG_RSRC_WORD0;
+
fprintf(f, COLOR_CYAN " Image:" COLOR_RESET "\n");
for (unsigned j = 0; j < 8; j++)
- ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
+ ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
desc[j], 0xffffffff);
fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
for (unsigned j = 0; j < 8; j++)
- ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
+ ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
desc[8 + j], 0xffffffff);
}
fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
fprintf(f, "\tdynamic_shader_stages: %x\n",
layout->dynamic_shader_stages);
+ fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
fprintf(f, "\tdynamic_offset_count: %d\n",
layout->dynamic_offset_count);
fprintf(f, "\n");
layout->binding[i].array_size);
fprintf(f, "\t\toffset: %d\n",
layout->binding[i].offset);
+ fprintf(f, "\t\tbuffer_offset: %d\n",
+ layout->binding[i].buffer_offset);
fprintf(f, "\t\tdynamic_offset_offset: %d\n",
layout->binding[i].dynamic_offset_offset);
fprintf(f, "\t\tdynamic_offset_count: %d\n",
}
static void
-radv_dump_annotated_shader(struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader,
- gl_shader_stage stage,
- struct ac_wave_info *waves, unsigned num_waves,
- FILE *f)
+radv_dump_annotated_shader(struct radv_shader_variant *shader,
+ gl_shader_stage stage, struct ac_wave_info *waves,
+ unsigned num_waves, FILE *f)
{
uint64_t start_addr, end_addr;
unsigned i;
start_addr, &num_inst, instructions);
fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
- radv_get_shader_name(shader, stage));
+ radv_get_shader_name(&shader->info, stage));
/* Print instructions with annotations. */
for (i = 0; i < num_inst; i++) {
static void
radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
- struct radv_shader_variant *compute_shader,
- FILE *f)
+ VkShaderStageFlagBits active_stages, FILE *f)
{
struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
- unsigned num_waves = ac_get_wave_info(waves);
- unsigned mask;
+ enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
+ unsigned num_waves = ac_get_wave_info(chip_class, waves);
fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
"\n\n", num_waves);
/* Dump annotated active graphics shaders. */
- mask = pipeline->active_stages;
- while (mask) {
- int stage = u_bit_scan(&mask);
+ while (active_stages) {
+ int stage = u_bit_scan(&active_stages);
- radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
+ radv_dump_annotated_shader(pipeline->shaders[stage],
stage, waves, num_waves, f);
}
- radv_dump_annotated_shader(pipeline, compute_shader,
- MESA_SHADER_COMPUTE, waves, num_waves, f);
-
/* Print waves executing shaders that are not currently bound. */
unsigned i;
bool found = false;
if (!shader)
return;
- fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
+ fprintf(f, "%s:\n\n", radv_get_shader_name(&shader->info, stage));
if (shader->spirv) {
- fprintf(f, "SPIRV:\n");
+ unsigned char sha1[21];
+ char sha1buf[41];
+
+ _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
+ _mesa_sha1_format(sha1buf, sha1);
+
+ fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
radv_print_spirv(shader->spirv, shader->spirv_size, f);
}
- if (shader->nir) {
- fprintf(f, "NIR:\n");
- nir_print_shader(shader->nir, f);
+ if (shader->nir_string) {
+ fprintf(f, "NIR:\n%s\n", shader->nir_string);
}
fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string);
static void
radv_dump_shaders(struct radv_pipeline *pipeline,
- struct radv_shader_variant *compute_shader, FILE *f)
+ VkShaderStageFlagBits active_stages, FILE *f)
{
- unsigned mask;
-
/* Dump active graphics shaders. */
- mask = pipeline->active_stages;
- while (mask) {
- int stage = u_bit_scan(&mask);
+ while (active_stages) {
+ int stage = u_bit_scan(&active_stages);
radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
}
+}
- radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
+static void
+radv_dump_pipeline_state(struct radv_pipeline *pipeline,
+ VkShaderStageFlagBits active_stages, FILE *f)
+{
+ radv_dump_shaders(pipeline, active_stages, f);
+ radv_dump_annotated_shaders(pipeline, active_stages, f);
+ radv_dump_descriptors(pipeline, f);
}
static void
radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
struct radv_pipeline *compute_pipeline, FILE *f)
{
- struct radv_shader_variant *compute_shader =
- compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
+ VkShaderStageFlagBits active_stages;
- if (!graphics_pipeline)
- return;
+ if (graphics_pipeline) {
+ active_stages = graphics_pipeline->active_stages;
+ radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
+ }
- radv_dump_shaders(graphics_pipeline, compute_shader, f);
- radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
- radv_dump_descriptors(graphics_pipeline, f);
+ if (compute_pipeline) {
+ active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
+ radv_dump_pipeline_state(compute_pipeline, active_stages, f);
+ }
}
static void
radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
{
+ VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
+
if (!compute_pipeline)
return;
- radv_dump_shaders(compute_pipeline,
- compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
- radv_dump_annotated_shaders(compute_pipeline,
- compute_pipeline->shaders[MESA_SHADER_COMPUTE],
- f);
- radv_dump_descriptors(compute_pipeline, f);
+ radv_dump_pipeline_state(compute_pipeline, active_stages, f);
}
static struct radv_pipeline *
radv_dump_device_name(struct radv_device *device, FILE *f)
{
struct radeon_info *info = &device->physical_device->rad_info;
- char llvm_string[32] = {}, kernel_version[128] = {};
+ char kernel_version[128] = {};
struct utsname uname_data;
const char *chip_name;
snprintf(kernel_version, sizeof(kernel_version),
" / %s", uname_data.release);
- if (HAVE_LLVM > 0) {
- snprintf(llvm_string, sizeof(llvm_string),
- ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
- HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
- }
-
- fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
+ fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
+ MESA_LLVM_VERSION_STRING ")\n\n",
chip_name, device->physical_device->name,
info->drm_major, info->drm_minor, info->drm_patchlevel,
- kernel_version, llvm_string);
+ kernel_version);
}
static bool
}
void
-radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
{
struct radv_pipeline *graphics_pipeline, *compute_pipeline;
struct radv_device *device = queue->device;
projects / mesa.git / blobdiff