#include <stdlib.h>
#include <stdio.h>
+#include <sys/utsname.h>
#include "sid.h"
#include "gfx9d.h"
device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
RADEON_DOMAIN_VRAM,
- RADEON_FLAG_CPU_ACCESS);
+ RADEON_FLAG_CPU_ACCESS|
+ RADEON_FLAG_NO_INTERPROCESS_SHARING);
if (!device->trace_bo)
return false;
struct ac_wave_info *waves, unsigned num_waves,
FILE *f)
{
- struct radv_device *device = pipeline->device;
uint64_t start_addr, end_addr;
unsigned i;
if (!shader)
return;
- start_addr = device->ws->buffer_get_va(shader->bo) + shader->bo_offset;
+ start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
end_addr = start_addr + shader->code_size;
/* See if any wave executes the shader. */
if (!shader)
return;
- fprintf(f, "%s:\n%s\n\n", radv_get_shader_name(shader, stage),
- shader->disasm_string);
+ fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
+
+ if (shader->spirv) {
+ fprintf(f, "SPIRV:\n");
+ radv_print_spirv(shader->spirv, shader->spirv_size, f);
+ }
+
+ if (shader->nir) {
+ fprintf(f, "NIR:\n");
+ nir_print_shader(shader->nir, f);
+ }
+
+ fprintf(f, "LLVM IR:\n%s\n", shader->llvm_ir_string);
+ fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
radv_shader_dump_stats(pipeline->device, shader, stage, f);
}
pclose(p);
}
-static void
+void
radv_dump_enabled_options(struct radv_device *device, FILE *f)
{
uint64_t mask;
- fprintf(f, "Enabled debug options: ");
+ if (device->instance->debug_flags) {
+ fprintf(f, "Enabled debug options: ");
- mask = device->debug_flags;
- while (mask) {
- int i = u_bit_scan64(&mask);
- fprintf(f, "%s, ", radv_get_debug_option_name(i));
+ mask = device->instance->debug_flags;
+ while (mask) {
+ int i = u_bit_scan64(&mask);
+ fprintf(f, "%s, ", radv_get_debug_option_name(i));
+ }
+ fprintf(f, "\n");
}
- fprintf(f, "\n");
- fprintf(f, "Enabled perftest options: ");
+ if (device->instance->perftest_flags) {
+ fprintf(f, "Enabled perftest options: ");
- mask = device->instance->perftest_flags;
- while (mask) {
- int i = u_bit_scan64(&mask);
- fprintf(f, "%s, ", radv_get_perftest_option_name(i));
+ mask = device->instance->perftest_flags;
+ while (mask) {
+ int i = u_bit_scan64(&mask);
+ fprintf(f, "%s, ", radv_get_perftest_option_name(i));
+ }
+ fprintf(f, "\n");
}
- fprintf(f, "\n");
+}
+
+static void
+radv_dump_device_name(struct radv_device *device, FILE *f)
+{
+ struct radeon_info *info = &device->physical_device->rad_info;
+ char llvm_string[32] = {}, kernel_version[128] = {};
+ struct utsname uname_data;
+ const char *chip_name;
+
+ chip_name = device->ws->get_chip_name(device->ws);
+
+ if (uname(&uname_data) == 0)
+ snprintf(kernel_version, sizeof(kernel_version),
+ " / %s", uname_data.release);
+
+ if (HAVE_LLVM > 0) {
+ snprintf(llvm_string, sizeof(llvm_string),
+ ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
+ HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
+ }
+
+ fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
+ chip_name, device->physical_device->name,
+ info->drm_major, info->drm_minor, info->drm_patchlevel,
+ kernel_version, llvm_string);
}
static bool
graphics_pipeline = radv_get_saved_graphics_pipeline(device);
compute_pipeline = radv_get_saved_compute_pipeline(device);
+ fprintf(stderr, "GPU hang report:\n\n");
+ radv_dump_device_name(device, stderr);
+
radv_dump_enabled_options(device, stderr);
radv_dump_dmesg(stderr);
}
void
-radv_print_spirv(struct radv_shader_module *module, FILE *fp)
+radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp)
{
char path[] = "/tmp/fileXXXXXX";
char line[2048], command[128];
if (fd < 0)
return;
- if (write(fd, module->data, module->size) == -1)
+ if (write(fd, data, size) == -1)
goto fail;
sprintf(command, "spirv-dis %s", path);