radv/gfx9: reduce the number of input VGPRs for the GS stage

[mesa.git] / src / amd / vulkan / radv_debug.c

diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index cb9509117eb712b280ab0693cbe68f6994b014d0..c8794d06ea8f26df9dcbece00fe15c1f07127c57 100644 (file)
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -61,7 +61,8 @@ radv_init_trace(struct radv_device *device)
 
        device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
                                             RADEON_DOMAIN_VRAM,
-                                            RADEON_FLAG_CPU_ACCESS);
+                                            RADEON_FLAG_CPU_ACCESS|
+                                            RADEON_FLAG_NO_INTERPROCESS_SHARING);
        if (!device->trace_bo)
                return false;
 
@@ -507,7 +508,7 @@ radv_dump_shader(struct radv_pipeline *pipeline,
                nir_print_shader(shader->nir, f);
        }
 
-       fprintf(stderr, "DISASM:\n%s\n", shader->disasm_string);
+       fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
 
        radv_shader_dump_stats(pipeline->device, shader, stage, f);
 }
@@ -599,7 +600,7 @@ radv_dump_enabled_options(struct radv_device *device, FILE *f)
 
        fprintf(f, "Enabled debug options: ");
 
-       mask = device->debug_flags;
+       mask = device->instance->debug_flags;
        while (mask) {
                int i = u_bit_scan64(&mask);
                fprintf(f, "%s, ", radv_get_debug_option_name(i));