radv/gfx10: enable vertex shaders without export parameters

[mesa.git] / src / amd / vulkan / radv_descriptor_set.h

diff --git a/src/amd/vulkan/radv_descriptor_set.h b/src/amd/vulkan/radv_descriptor_set.h
index c373489ccb3d9fb2a55ed9dd7cab0f114d9ede8d..89be6e69068f2a72de64969638eeaadd51c42cf2 100644 (file)
--- a/src/amd/vulkan/radv_descriptor_set.h
+++ b/src/amd/vulkan/radv_descriptor_set.h
@@ -26,45 +26,56 @@
 
 #include <vulkan/vulkan.h>
 
-#define MAX_SETS         8
+#define MAX_SETS         32
 
 struct radv_descriptor_set_binding_layout {
    VkDescriptorType type;
 
    /* Number of array elements in this binding */
-   uint16_t array_size;
+   uint32_t array_size;
 
-   uint16_t offset;
-   uint16_t buffer_offset;
+   uint32_t offset;
+   uint32_t buffer_offset;
    uint16_t dynamic_offset_offset;
 
-   /* redundant with the type, each for a single array element */
-   uint16_t size;
-   uint16_t buffer_count;
    uint16_t dynamic_offset_count;
+   /* redundant with the type, each for a single array element */
+   uint32_t size;
 
-   /* Immutable samplers (or NULL if no immutable samplers) */
-   uint32_t *immutable_samplers;
+   /* Offset in the radv_descriptor_set_layout of the immutable samplers, or 0
+    * if there are no immutable samplers. */
+   uint32_t immutable_samplers_offset;
    bool immutable_samplers_equal;
 };
 
 struct radv_descriptor_set_layout {
+   /* The create flags for this descriptor set layout */
+   VkDescriptorSetLayoutCreateFlags flags;
+
    /* Number of bindings in this descriptor set */
-   uint16_t binding_count;
+   uint32_t binding_count;
 
    /* Total size of the descriptor set with room for all array entries */
-   uint16_t size;
+   uint32_t size;
+
+   /* CPU size of this struct + all associated data, for hashing. */
+   uint32_t layout_size;
 
    /* Shader stages affected by this descriptor set */
    uint16_t shader_stages;
    uint16_t dynamic_shader_stages;
 
    /* Number of buffers in this descriptor set */
-   uint16_t buffer_count;
+   uint32_t buffer_count;
 
    /* Number of dynamic offsets used by this descriptor set */
    uint16_t dynamic_offset_count;
 
+   bool has_immutable_samplers;
+   bool has_variable_descriptors;
+
+   uint32_t ycbcr_sampler_offsets_offset;
+
    /* Bindings in this descriptor set */
    struct radv_descriptor_set_binding_layout binding[0];
 };
@@ -79,8 +90,34 @@ struct radv_pipeline_layout {
    uint32_t num_sets;
    uint32_t push_constant_size;
    uint32_t dynamic_offset_count;
+   uint16_t dynamic_shader_stages;
 
    unsigned char sha1[20];
 };
 
+static inline const uint32_t *
+radv_immutable_samplers(const struct radv_descriptor_set_layout *set,
+                        const struct radv_descriptor_set_binding_layout *binding) {
+       return (const uint32_t*)((const char*)set + binding->immutable_samplers_offset);
+}
+
+static inline unsigned
+radv_combined_image_descriptor_sampler_offset(const struct radv_descriptor_set_binding_layout *binding)
+{
+       return binding->size - ((!binding->immutable_samplers_equal) ? 16 : 0);
+}
+
+static inline const struct radv_sampler_ycbcr_conversion *
+radv_immutable_ycbcr_samplers(const struct radv_descriptor_set_layout *set,
+                              unsigned binding_index)
+{
+       if (!set->ycbcr_sampler_offsets_offset)
+               return NULL;
+
+       const uint32_t *offsets = (const uint32_t*)((const char*)set + set->ycbcr_sampler_offsets_offset);
+
+       if (offsets[binding_index] == 0)
+               return NULL;
+       return (const struct radv_sampler_ycbcr_conversion *)((const char*)set + offsets[binding_index]);
+}
 #endif /* RADV_DESCRIPTOR_SET_H */