radv: fix descriptor pool allocation size

[mesa.git] / src / amd / vulkan / radv_descriptor_set.h

diff --git a/src/amd/vulkan/radv_descriptor_set.h b/src/amd/vulkan/radv_descriptor_set.h
index cad1ccf1573be1cdfd1a88d3ae7a558f0e127586..d8431241fd917c11420864e72f30f77a152b1759 100644 (file)
--- a/src/amd/vulkan/radv_descriptor_set.h
+++ b/src/amd/vulkan/radv_descriptor_set.h
@@ -1,6 +1,6 @@
 /*
  * Copyright © 2016 Bas Nieuwenhuizen
-  *
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
@@ -20,48 +20,57 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
-#pragma once
+
+#ifndef RADV_DESCRIPTOR_SET_H
+#define RADV_DESCRIPTOR_SET_H
 
 #include <vulkan/vulkan.h>
 
-#define MAX_SETS         8
+#define MAX_SETS         32
 
 struct radv_descriptor_set_binding_layout {
    VkDescriptorType type;
 
    /* Number of array elements in this binding */
-   uint16_t array_size;
+   uint32_t array_size;
 
-   uint16_t offset;
-   uint16_t buffer_offset;
+   uint32_t offset;
+   uint32_t buffer_offset;
    uint16_t dynamic_offset_offset;
 
-   /* redundant with the type, each for a single array element */
-   uint16_t size;
-   uint16_t buffer_count;
    uint16_t dynamic_offset_count;
+   /* redundant with the type, each for a single array element */
+   uint32_t size;
 
-   /* Immutable samplers (or NULL if no immutable samplers) */
-   struct radv_sampler **immutable_samplers;
+   /* Offset in the radv_descriptor_set_layout of the immutable samplers, or 0
+    * if there are no immutable samplers. */
+   uint32_t immutable_samplers_offset;
+   bool immutable_samplers_equal;
 };
 
 struct radv_descriptor_set_layout {
+   /* The create flags for this descriptor set layout */
+   VkDescriptorSetLayoutCreateFlags flags;
+
    /* Number of bindings in this descriptor set */
-   uint16_t binding_count;
+   uint32_t binding_count;
 
    /* Total size of the descriptor set with room for all array entries */
-   uint16_t size;
+   uint32_t size;
 
    /* Shader stages affected by this descriptor set */
    uint16_t shader_stages;
    uint16_t dynamic_shader_stages;
 
    /* Number of buffers in this descriptor set */
-   uint16_t buffer_count;
+   uint32_t buffer_count;
 
    /* Number of dynamic offsets used by this descriptor set */
    uint16_t dynamic_offset_count;
 
+   bool has_immutable_samplers;
+   bool has_variable_descriptors;
+
    /* Bindings in this descriptor set */
    struct radv_descriptor_set_binding_layout binding[0];
 };
@@ -79,3 +88,10 @@ struct radv_pipeline_layout {
 
    unsigned char sha1[20];
 };
+
+static inline const uint32_t *
+radv_immutable_samplers(const struct radv_descriptor_set_layout *set,
+                        const struct radv_descriptor_set_binding_layout *binding) {
+       return (const uint32_t*)((const char*)set + binding->immutable_samplers_offset);
+}
+#endif /* RADV_DESCRIPTOR_SET_H */