radv/gfx10: set the DCC constant encoding flag

[mesa.git] / src / amd / vulkan / radv_device.c

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d22c43b1098247a4fdf2877f813a070161155628..2d5e5f511e02fe777acf2e4601fff79f822b3e8b 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -376,7 +376,8 @@ radv_physical_device_init(struct radv_physical_device *device,
                                       (device->rad_info.chip_class >= GFX8 &&
                                        device->rad_info.me_fw_feature >= 41);
 
-       device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2;
+       device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
+                                         device->rad_info.chip_class >= GFX10;
 
        device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
 
@@ -2159,12 +2160,19 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(1) |
                          S_008F0C_INDEX_STRIDE(3) |
                          S_008F0C_ADD_TID_ENABLE(true);
 
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
+
                /* GS entry for ES->GS ring */
                /* stride 0, num records - size, elsize0,
                   index stride 0 */
@@ -2177,11 +2185,18 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(0) |
                          S_008F0C_INDEX_STRIDE(0) |
                          S_008F0C_ADD_TID_ENABLE(false);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
        }
 
        desc += 8;
@@ -2201,12 +2216,19 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(0) |
                          S_008F0C_INDEX_STRIDE(0) |
                          S_008F0C_ADD_TID_ENABLE(false);
 
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
+
                /* stride gsvs_itemsize, num records 64
                   elsize 4, index stride 16 */
                /* shader will patch stride and desc[2] */
@@ -2219,11 +2241,19 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(1) |
                          S_008F0C_INDEX_STRIDE(1) |
                          S_008F0C_ADD_TID_ENABLE(true);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
+
        }
 
        desc += 8;
@@ -2240,12 +2270,16 @@ fill_geom_tess_rings(struct radv_queue *queue,
                desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
-                         S_008F0C_ELEMENT_SIZE(0) |
-                         S_008F0C_INDEX_STRIDE(0) |
-                         S_008F0C_ADD_TID_ENABLE(false);
+                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(3) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
 
                desc[4] = tess_offchip_va;
                desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
@@ -2255,12 +2289,16 @@ fill_geom_tess_rings(struct radv_queue *queue,
                desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
-                         S_008F0C_ELEMENT_SIZE(0) |
-                         S_008F0C_INDEX_STRIDE(0) |
-                         S_008F0C_ADD_TID_ENABLE(false);
+                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(3) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
        }
 
        desc += 8;
@@ -4386,8 +4424,11 @@ radv_initialise_color_surface(struct radv_device *device,
            device->physical_device->rad_info.chip_class <= GFX8)
                va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
 
+       unsigned dcc_tile_swizzle = surf->tile_swizzle;
+       dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
+
        cb->cb_dcc_base = va >> 8;
-       cb->cb_dcc_base |= surf->tile_swizzle;
+       cb->cb_dcc_base |= dcc_tile_swizzle;
 
        /* GFX10 field has the same base shift as the GFX6 field. */
        uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;