radv: fix descriptor pool allocation size

[mesa.git] / src / amd / vulkan / radv_device.c

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 79dbbd886d51fca21f4ce99c45d441a1c7a95a2e..8989ec3553fbf78bcf98765612b786bbde53a045 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -821,6 +821,13 @@ void radv_GetPhysicalDeviceFeatures2(
                        features->inheritedConditionalRendering = false;
                        break;
                }
+               case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
+                       VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
+                               (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
+                       features->vertexAttributeInstanceRateDivisor = VK_TRUE;
+                       features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
+                       break;
+               }
                default:
                        break;
                }
@@ -1139,6 +1146,12 @@ void radv_GetPhysicalDeviceProperties2(
                        properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
                        break;
                }
+               case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
+                       VkPhysicalDeviceProtectedMemoryProperties *properties =
+                               (VkPhysicalDeviceProtectedMemoryProperties *)ext;
+                       properties->protectedNoFault = false;
+                       break;
+               }
                default:
                        break;
                }
@@ -1895,10 +1908,30 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff
                device->physical_device->rad_info.family != CHIP_CARRIZO &&
                device->physical_device->rad_info.family != CHIP_STONEY;
        unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
-       unsigned max_offchip_buffers = max_offchip_buffers_per_se *
-               device->physical_device->rad_info.max_se;
+       unsigned max_offchip_buffers;
        unsigned offchip_granularity;
        unsigned hs_offchip_param;
+
+       /*
+        * Per RadeonSI:
+        * This must be one less than the maximum number due to a hw limitation.
+         * Various hardware bugs in SI, CIK, and GFX9 need this.
+        *
+        * Per AMDVLK:
+        * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
+        * Gfx7 should limit max_offchip_buffers to 508
+        * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
+        *
+        * Follow AMDVLK here.
+        */
+       if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
+           device->physical_device->rad_info.chip_class == CIK ||
+           device->physical_device->rad_info.chip_class == SI)
+               --max_offchip_buffers_per_se;
+
+       max_offchip_buffers = max_offchip_buffers_per_se *
+               device->physical_device->rad_info.max_se;
+
        switch (device->tess_offchip_block_dw_size) {
        default:
                assert(0);
@@ -2057,6 +2090,33 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
        }
 }
 
+static void
+radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
+{
+       struct radv_device *device = queue->device;
+
+       if (device->gfx_init) {
+               uint64_t va = radv_buffer_get_va(device->gfx_init);
+
+               radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
+               radeon_emit(cs, va);
+               radeon_emit(cs, va >> 32);
+               radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
+
+               radv_cs_add_buffer(device->ws, cs, device->gfx_init);
+       } else {
+               struct radv_physical_device *physical_device = device->physical_device;
+               si_emit_graphics(physical_device, cs);
+       }
+}
+
+static void
+radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
+{
+       struct radv_physical_device *physical_device = queue->device->physical_device;
+       si_emit_compute(physical_device, cs);
+}
+
 static VkResult
 radv_get_preamble_cs(struct radv_queue *queue,
                      uint32_t scratch_size,
@@ -2211,6 +2271,18 @@ radv_get_preamble_cs(struct radv_queue *queue,
                if (scratch_bo)
                        radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
 
+               /* Emit initial configuration. */
+               switch (queue->queue_family_index) {
+               case RADV_QUEUE_GENERAL:
+                       radv_init_graphics_state(cs, queue);
+                       break;
+               case RADV_QUEUE_COMPUTE:
+                       radv_init_compute_state(cs, queue);
+                       break;
+               case RADV_QUEUE_TRANSFER:
+                       break;
+               }
+
                if (descriptor_bo != queue->descriptor_bo) {
                        uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);