projects / mesa.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
radv/gfx10: disable geometry and tessellation shaders
[mesa.git] / src / amd / vulkan / radv_device.c
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8a89ad473f51e64400aa1ffc58cdccef597cd33e..d111ab6b130bc87feeed95bc36701e1918944ecd 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -354,7 +354,8 @@ radv_physical_device_init(struct radv_physical_device *device,
        /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
         * on GFX6.
         */
-       device->has_clear_state = device->rad_info.chip_class >= GFX7;
+       device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
+                                 device->rad_info.chip_class <= GFX9;
 
        device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
 
@@ -376,7 +377,8 @@ radv_physical_device_init(struct radv_physical_device *device,
                                       (device->rad_info.chip_class >= GFX8 &&
                                        device->rad_info.me_fw_feature >= 41);
 
-       device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2;
+       device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
+                                         device->rad_info.chip_class >= GFX10;
 
        device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
 
@@ -760,8 +762,8 @@ void radv_GetPhysicalDeviceFeatures(
                .fullDrawIndexUint32                      = true,
                .imageCubeArray                           = true,
                .independentBlend                         = true,
-               .geometryShader                           = true,
-               .tessellationShader                       = true,
+               .geometryShader                           = pdevice->rad_info.chip_class < GFX10,
+               .tessellationShader                       = pdevice->rad_info.chip_class < GFX10,
                .sampleRateShading                        = true,
                .dualSrcBlend                             = true,
                .logicOp                                  = true,
@@ -1895,7 +1897,8 @@ VkResult radv_CreateDevice(
                }
        }
 
-       device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
+       /* TODO: Enable binning for GFX10. */
+       device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
                              !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
 
        /* Disabled and not implemented for now. */
@@ -2159,12 +2162,19 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(1) |
                          S_008F0C_INDEX_STRIDE(3) |
                          S_008F0C_ADD_TID_ENABLE(true);
 
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
+
                /* GS entry for ES->GS ring */
                /* stride 0, num records - size, elsize0,
                   index stride 0 */
@@ -2177,11 +2187,18 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(0) |
                          S_008F0C_INDEX_STRIDE(0) |
                          S_008F0C_ADD_TID_ENABLE(false);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
        }
 
        desc += 8;
@@ -2201,12 +2218,19 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(0) |
                          S_008F0C_INDEX_STRIDE(0) |
                          S_008F0C_ADD_TID_ENABLE(false);
 
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
+
                /* stride gsvs_itemsize, num records 64
                   elsize 4, index stride 16 */
                /* shader will patch stride and desc[2] */
@@ -2219,11 +2243,19 @@ fill_geom_tess_rings(struct radv_queue *queue,
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
                          S_008F0C_ELEMENT_SIZE(1) |
                          S_008F0C_INDEX_STRIDE(1) |
                          S_008F0C_ADD_TID_ENABLE(true);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(2) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
+
        }
 
        desc += 8;
@@ -2240,12 +2272,16 @@ fill_geom_tess_rings(struct radv_queue *queue,
                desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
-                         S_008F0C_ELEMENT_SIZE(0) |
-                         S_008F0C_INDEX_STRIDE(0) |
-                         S_008F0C_ADD_TID_ENABLE(false);
+                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(3) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
 
                desc[4] = tess_offchip_va;
                desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
@@ -2255,12 +2291,16 @@ fill_geom_tess_rings(struct radv_queue *queue,
                desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                          S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                          S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-                         S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
-                         S_008F0C_ELEMENT_SIZE(0) |
-                         S_008F0C_INDEX_STRIDE(0) |
-                         S_008F0C_ADD_TID_ENABLE(false);
+                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+               if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
+                       desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+                                  S_008F0C_OOB_SELECT(3) |
+                                  S_008F0C_RESOURCE_LEVEL(1);
+               } else {
+                       desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+               }
        }
 
        desc += 8;
@@ -4386,8 +4426,11 @@ radv_initialise_color_surface(struct radv_device *device,
            device->physical_device->rad_info.chip_class <= GFX8)
                va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
 
+       unsigned dcc_tile_swizzle = surf->tile_swizzle;
+       dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
+
        cb->cb_dcc_base = va >> 8;
-       cb->cb_dcc_base |= surf->tile_swizzle;
+       cb->cb_dcc_base |= dcc_tile_swizzle;
 
        /* GFX10 field has the same base shift as the GFX6 field. */
        uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
@@ -4938,7 +4981,8 @@ radv_init_sampler(struct radv_device *device,
 {
        uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
        uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
-       bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
+       bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
+                          device->physical_device->rad_info.chip_class == GFX9;
        unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
 
        const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
@@ -4956,7 +5000,7 @@ radv_init_sampler(struct radv_device *device,
                             S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
                             S_008F30_ANISO_BIAS(max_aniso_ratio) |
                             S_008F30_DISABLE_CUBE_WRAP(0) |
-                            S_008F30_COMPAT_MODE(is_vi) |
+                            S_008F30_COMPAT_MODE(compat_mode) |
                             S_008F30_FILTER_MODE(filter_mode));
        sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
                             S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
@@ -4965,12 +5009,18 @@ radv_init_sampler(struct radv_device *device,
                             S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
                             S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
                             S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
-                            S_008F38_MIP_POINT_PRECLAMP(0) |
-                            S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
-                            S_008F38_FILTER_PREC_FIX(1) |
-                            S_008F38_ANISO_OVERRIDE_GFX6(is_vi));
+                            S_008F38_MIP_POINT_PRECLAMP(0));
        sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
                             S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
+
+       if (device->physical_device->rad_info.chip_class >= GFX10) {
+               sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
+       } else {
+               sampler->state[2] |=
+                       S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
+                       S_008F38_FILTER_PREC_FIX(1) |
+                       S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
+       }
 }
 
 VkResult radv_CreateSampler(