}
static bool
-radv_image_is_tc_compat_htile(struct radv_device *device,
- const VkImageCreateInfo *pCreateInfo)
+radv_use_tc_compat_htile_for_image(struct radv_device *device,
+ const VkImageCreateInfo *pCreateInfo)
{
/* TC-compat HTILE is only available for GFX8+. */
if (device->physical_device->rad_info.chip_class < VI)
return true;
}
+static bool
+radv_use_dcc_for_image(struct radv_device *device,
+ const struct radv_image_create_info *create_info,
+ const VkImageCreateInfo *pCreateInfo)
+{
+ bool dcc_compatible_formats;
+ bool blendable;
+ bool shareable = vk_find_struct_const(pCreateInfo->pNext,
+ EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
+
+ /* DCC (Delta Color Compression) is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < VI)
+ return false;
+
+ if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
+ return false;
+
+ /* FIXME: DCC is broken for shareable images starting with GFX9 */
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ shareable)
+ return false;
+
+ /* TODO: Enable DCC for storage images. */
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
+ (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
+ return false;
+
+ if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
+ return false;
+
+ /* TODO: Enable DCC for mipmaps and array layers. */
+ if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
+ return false;
+
+ if (create_info->scanout)
+ return false;
+
+ /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
+ * 2x can be enabled with an option.
+ */
+ if (pCreateInfo->samples > 2 ||
+ (pCreateInfo->samples == 2 &&
+ !device->physical_device->dcc_msaa_allowed))
+ return false;
+
+ /* Determine if the formats are DCC compatible. */
+ dcc_compatible_formats =
+ radv_is_colorbuffer_format_supported(pCreateInfo->format,
+ &blendable);
+
+ if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
+ const struct VkImageFormatListCreateInfoKHR *format_list =
+ (const struct VkImageFormatListCreateInfoKHR *)
+ vk_find_struct_const(pCreateInfo->pNext,
+ IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+
+ /* We have to ignore the existence of the list if viewFormatCount = 0 */
+ if (format_list && format_list->viewFormatCount) {
+ /* compatibility is transitive, so we only need to check
+ * one format with everything else. */
+ for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
+ if (!radv_dcc_formats_compatible(pCreateInfo->format,
+ format_list->pViewFormats[i]))
+ dcc_compatible_formats = false;
+ }
+ } else {
+ dcc_compatible_formats = false;
+ }
+ }
+
+ if (!dcc_compatible_formats)
+ return false;
+
+ return true;
+}
+
static int
radv_init_surface(struct radv_device *device,
struct radeon_surf *surface,
unsigned array_mode = radv_choose_tiling(device, create_info);
const struct vk_format_description *desc =
vk_format_description(pCreateInfo->format);
- bool is_depth, is_stencil, blendable;
+ bool is_depth, is_stencil;
is_depth = vk_format_has_depth(desc);
is_stencil = vk_format_has_stencil(desc);
if (is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
- if (radv_image_is_tc_compat_htile(device, pCreateInfo))
+ if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- bool dcc_compatible_formats = radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
- if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
- const struct VkImageFormatListCreateInfoKHR *format_list =
- (const struct VkImageFormatListCreateInfoKHR *)
- vk_find_struct_const(pCreateInfo->pNext,
- IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
-
- /* We have to ignore the existence of the list if viewFormatCount = 0 */
- if (format_list && format_list->viewFormatCount) {
- /* compatibility is transitive, so we only need to check
- * one format with everything else. */
- for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
- if (!radv_dcc_formats_compatible(pCreateInfo->format,
- format_list->pViewFormats[i]))
- dcc_compatible_formats = false;
- }
- } else {
- dcc_compatible_formats = false;
- }
- }
-
- if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
- (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
- !dcc_compatible_formats ||
- (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
- pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
- device->physical_device->rad_info.chip_class < VI ||
- create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC) ||
- pCreateInfo->samples >= 2)
+ if (!radv_use_dcc_for_image(device, create_info, pCreateInfo))
surface->flags |= RADEON_SURF_DISABLE_DCC;
+
if (create_info->scanout)
surface->flags |= RADEON_SURF_SCANOUT;
return 0;
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if(!is_storage_image && image->tc_compatible_htile &&
- radv_image_has_htile(image)) {
+ } else if (!is_storage_image &&
+ radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
}
else
return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
default:
- unreachable("illegale image type");
+ unreachable("illegal image type");
}
}
/* S8 with either Z16 or Z32 HTILE need a special format. */
if (device->physical_device->rad_info.chip_class >= GFX9 &&
vk_format == VK_FORMAT_S8_UINT &&
- image->tc_compatible_htile) {
+ radv_image_is_tc_compat_htile(image)) {
if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
if (device->physical_device->rad_info.chip_class >= GFX9) {
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
- /* Depth is the the last accessible layer on Gfx9.
+ /* Depth is the last accessible layer on Gfx9.
* The hw doesn't need to know the total number of layers.
*/
if (type == V_008F1C_SQ_RSRC_IMG_3D)
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
- S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
+ S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
fmask_state[4] = 0;
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;
unsigned nr_samples,
struct radv_fmask_info *out)
{
- /* FMASK is allocated like an ordinary texture. */
- struct radeon_surf fmask = {};
- struct ac_surf_info info = image->info;
- memset(out, 0, sizeof(*out));
-
if (device->physical_device->rad_info.chip_class >= GFX9) {
- out->alignment = image->surface.u.gfx9.fmask_alignment;
- out->size = image->surface.u.gfx9.fmask_size;
+ out->alignment = image->surface.fmask_alignment;
+ out->size = image->surface.fmask_size;
+ out->tile_swizzle = image->surface.fmask_tile_swizzle;
return;
}
- fmask.blk_w = image->surface.blk_w;
- fmask.blk_h = image->surface.blk_h;
- info.samples = 1;
- fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
-
- if (!image->shareable)
- info.surf_index = &device->fmask_mrt_offset_counter;
-
- /* Force 2D tiling if it wasn't set. This may occur when creating
- * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
- * destination buffer must have an FMASK too. */
- fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
- fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-
- switch (nr_samples) {
- case 2:
- case 4:
- fmask.bpe = 1;
- break;
- case 8:
- fmask.bpe = 4;
- break;
- default:
- return;
- }
-
- device->ws->surface_init(device->ws, &info, &fmask);
- assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
-
- out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
- if (out->slice_tile_max)
- out->slice_tile_max -= 1;
-
- out->tile_mode_index = fmask.u.legacy.tiling_index[0];
- out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
- out->bank_height = fmask.u.legacy.bankh;
- out->tile_swizzle = fmask.tile_swizzle;
- out->alignment = MAX2(256, fmask.surf_alignment);
- out->size = fmask.surf_size;
+ out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
+ out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
+ out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
+ out->bank_height = image->surface.u.legacy.fmask.bankh;
+ out->tile_swizzle = image->surface.fmask_tile_swizzle;
+ out->alignment = image->surface.fmask_alignment;
+ out->size = image->surface.fmask_size;
assert(!out->tile_swizzle || !image->shareable);
}
image->info.height = pCreateInfo->extent.height;
image->info.depth = pCreateInfo->extent.depth;
image->info.samples = pCreateInfo->samples;
+ image->info.color_samples = pCreateInfo->samples;
image->info.array_size = pCreateInfo->arrayLayers;
image->info.levels = pCreateInfo->mipLevels;
+ image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
image->vk_format = pCreateInfo->format;
image->tiling = pCreateInfo->tiling;
/* Try to enable DCC first. */
if (radv_image_can_enable_dcc(image)) {
radv_image_alloc_dcc(image);
+ if (image->info.samples > 1) {
+ /* CMASK should be enabled because DCC fast
+ * clear with MSAA needs it.
+ */
+ assert(radv_image_can_enable_cmask(image));
+ radv_image_alloc_cmask(device, image);
+ }
} else {
/* When DCC cannot be enabled, try CMASK. */
image->surface.dcc_size = 0;
VkImageLayout layout,
unsigned queue_mask)
{
- if (radv_image_has_htile(image) && image->tc_compatible_htile)
+ if (radv_image_is_tc_compat_htile(image))
return layout != VK_IMAGE_LAYOUT_GENERAL;
return radv_image_has_htile(image) &&
VkImageLayout layout,
unsigned queue_mask)
{
- if (radv_image_has_htile(image) && image->tc_compatible_htile)
+ if (radv_image_is_tc_compat_htile(image))
return layout != VK_IMAGE_LAYOUT_GENERAL;
return radv_image_has_htile(image) &&
(queue_mask & (1u << RADV_QUEUE_COMPUTE)))
return false;
- return image->surface.num_dcc_levels > 0 && layout != VK_IMAGE_LAYOUT_GENERAL;
+ return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
}
projects / mesa.git / blobdiff