radv/gfx10: do not set ELEMENT_SIZE for buffer descriptors

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 644e3f0a0f94f8baf684cba0257608819d365d0c..09413333cbb21fd6d7e927d7a34211ffd8556e9c 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -83,9 +83,12 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
                return false;
 
        /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
-        * tests - disable for now */
+        * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
+        */
        if (pCreateInfo->samples >= 2 &&
-           pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
+           (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
+            (pCreateInfo->format == VK_FORMAT_D32_SFLOAT &&
+             device->physical_device->rad_info.chip_class == GFX10)))
                return false;
 
        /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
@@ -404,12 +407,6 @@ radv_make_buffer_descriptor(struct radv_device *device,
        first_non_void = vk_format_get_first_non_void_channel(vk_format);
        stride = desc->block.bits / 8;
 
-       num_format = radv_translate_buffer_numformat(desc, first_non_void);
-       data_format = radv_translate_buffer_dataformat(desc, first_non_void);
-
-       assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
-       assert(num_format != ~0);
-
        va += offset;
        state[0] = va;
        state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
@@ -423,9 +420,31 @@ radv_make_buffer_descriptor(struct radv_device *device,
        state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
                   S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
                   S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
-                  S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
-                  S_008F0C_NUM_FORMAT(num_format) |
-                  S_008F0C_DATA_FORMAT(data_format);
+                  S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
+
+       if (device->physical_device->rad_info.chip_class >= GFX10) {
+               const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
+
+               /* OOB_SELECT chooses the out-of-bounds check:
+                *  - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
+                *  - 1: index >= NUM_RECORDS
+                *  - 2: NUM_RECORDS == 0
+                *  - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
+                *       else: swizzle_address >= NUM_RECORDS
+                */
+               state[3] |= S_008F0C_FORMAT(fmt->img_format) |
+                           S_008F0C_OOB_SELECT(0) |
+                           S_008F0C_RESOURCE_LEVEL(1);
+       } else {
+               num_format = radv_translate_buffer_numformat(desc, first_non_void);
+               data_format = radv_translate_buffer_dataformat(desc, first_non_void);
+
+               assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
+               assert(num_format != ~0);
+
+               state[3] |= S_008F0C_NUM_FORMAT(num_format) |
+                           S_008F0C_DATA_FORMAT(data_format);
+       }
 }
 
 static void
@@ -503,7 +522,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                }
 
                state[7] = meta_va >> 16;
-       } else if (chip_class >= GFX9) {
+       } else if (chip_class == GFX9) {
                state[3] &= C_008F1C_SW_MODE;
                state[4] &= C_008F20_PITCH;
 
@@ -630,7 +649,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
        }
 
        type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
-                           is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
+                           is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
        if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
                height = 1;
                depth = image->info.array_size;
@@ -768,7 +787,7 @@ si_make_texture_descriptor(struct radv_device *device,
        }
 
        /* S8 with either Z16 or Z32 HTILE need a special format. */
-       if (device->physical_device->rad_info.chip_class >= GFX9 &&
+       if (device->physical_device->rad_info.chip_class == GFX9 &&
            vk_format == VK_FORMAT_S8_UINT &&
            radv_image_is_tc_compat_htile(image)) {
                if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
@@ -777,7 +796,7 @@ si_make_texture_descriptor(struct radv_device *device,
                        data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
        }
        type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
-                           is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
+                           is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
        if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
                height = 1;
                depth = image->info.array_size;
@@ -809,7 +828,7 @@ si_make_texture_descriptor(struct radv_device *device,
        state[6] = 0;
        state[7] = 0;
 
-       if (device->physical_device->rad_info.chip_class >= GFX9) {
+       if (device->physical_device->rad_info.chip_class == GFX9) {
                unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
 
                /* Depth is the last accessible layer on Gfx9.
@@ -855,7 +874,7 @@ si_make_texture_descriptor(struct radv_device *device,
 
                va = gpu_address + image->offset + image->fmask.offset;
 
-               if (device->physical_device->rad_info.chip_class >= GFX9) {
+               if (device->physical_device->rad_info.chip_class == GFX9) {
                        fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
                        switch (image->info.samples) {
                        case 2:
@@ -905,7 +924,7 @@ si_make_texture_descriptor(struct radv_device *device,
                fmask_state[6] = 0;
                fmask_state[7] = 0;
 
-               if (device->physical_device->rad_info.chip_class >= GFX9) {
+               if (device->physical_device->rad_info.chip_class == GFX9) {
                        fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
                        fmask_state[4] |= S_008F20_DEPTH(last_layer) |
                                          S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
@@ -1137,6 +1156,11 @@ radv_image_alloc_cmask(struct radv_device *device,
        uint32_t clear_value_size = 0;
        radv_image_get_cmask_info(device, image, &image->cmask);
 
+       if (!image->cmask.size)
+               return;
+
+       assert(image->cmask.alignment);
+
        image->cmask.offset = align64(image->size, image->cmask.alignment);
        /* + 8 for storing the clear values */
        if (!image->clear_value_offset) {
@@ -1162,14 +1186,15 @@ radv_image_alloc_dcc(struct radv_image *image)
 }
 
 static void
-radv_image_alloc_htile(struct radv_image *image)
+radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
 {
        image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
 
        /* + 8 for storing the clear values */
        image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
        image->size = image->clear_value_offset + 8;
-       if (radv_image_is_tc_compat_htile(image)) {
+       if (radv_image_is_tc_compat_htile(image) &&
+           device->physical_device->has_tc_compat_zrange_bug) {
                /* Metadata for the TC-compatible HTILE hardware bug which
                 * have to be fixed by updating ZRANGE_PRECISION when doing
                 * fast depth clears to 0.0f.
@@ -1378,7 +1403,7 @@ radv_image_create(VkDevice _device,
                        if (radv_image_can_enable_htile(image) &&
                            !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
                                image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
-                               radv_image_alloc_htile(image);
+                               radv_image_alloc_htile(device, image);
                        } else {
                                radv_image_disable_htile(image);
                        }