{
bool dcc_compatible_formats;
bool blendable;
+ bool shareable = vk_find_struct_const(pCreateInfo->pNext,
+ EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
/* DCC (Delta Color Compression) is only available for GFX8+. */
if (device->physical_device->rad_info.chip_class < VI)
if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
return false;
+ /* FIXME: DCC is broken for shareable images starting with GFX9 */
+ if (device->physical_device->rad_info.chip_class >= GFX9 &&
+ shareable)
+ return false;
+
/* TODO: Enable DCC for storage images. */
if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
else
return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
default:
- unreachable("illegale image type");
+ unreachable("illegal image type");
}
}
if (device->physical_device->rad_info.chip_class >= GFX9) {
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
- /* Depth is the the last accessible layer on Gfx9.
+ /* Depth is the last accessible layer on Gfx9.
* The hw doesn't need to know the total number of layers.
*/
if (type == V_008F1C_SQ_RSRC_IMG_3D)
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
- S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
+ S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
fmask_state[4] = 0;
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;
unsigned nr_samples,
struct radv_fmask_info *out)
{
- /* FMASK is allocated like an ordinary texture. */
- struct radeon_surf fmask = {};
- struct ac_surf_info info = image->info;
- memset(out, 0, sizeof(*out));
-
if (device->physical_device->rad_info.chip_class >= GFX9) {
- out->alignment = image->surface.u.gfx9.fmask_alignment;
- out->size = image->surface.u.gfx9.fmask_size;
- return;
- }
-
- fmask.blk_w = image->surface.blk_w;
- fmask.blk_h = image->surface.blk_h;
- info.samples = 1;
- fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
-
- if (!image->shareable)
- info.surf_index = &device->fmask_mrt_offset_counter;
-
- /* Force 2D tiling if it wasn't set. This may occur when creating
- * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
- * destination buffer must have an FMASK too. */
- fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
- fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-
- switch (nr_samples) {
- case 2:
- case 4:
- fmask.bpe = 1;
- break;
- case 8:
- fmask.bpe = 4;
- break;
- default:
+ out->alignment = image->surface.fmask_alignment;
+ out->size = image->surface.fmask_size;
+ out->tile_swizzle = image->surface.fmask_tile_swizzle;
return;
}
- device->ws->surface_init(device->ws, &info, &fmask);
- assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
-
- out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
- if (out->slice_tile_max)
- out->slice_tile_max -= 1;
-
- out->tile_mode_index = fmask.u.legacy.tiling_index[0];
- out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
- out->bank_height = fmask.u.legacy.bankh;
- out->tile_swizzle = fmask.tile_swizzle;
- out->alignment = MAX2(256, fmask.surf_alignment);
- out->size = fmask.surf_size;
+ out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
+ out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
+ out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
+ out->bank_height = image->surface.u.legacy.fmask.bankh;
+ out->tile_swizzle = image->surface.fmask_tile_swizzle;
+ out->alignment = image->surface.fmask_alignment;
+ out->size = image->surface.fmask_size;
assert(!out->tile_swizzle || !image->shareable);
}
image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!image)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
image->type = pCreateInfo->imageType;
image->info.width = pCreateInfo->extent.width;
image->info.height = pCreateInfo->extent.height;
image->info.depth = pCreateInfo->extent.depth;
image->info.samples = pCreateInfo->samples;
+ image->info.color_samples = pCreateInfo->samples;
image->info.array_size = pCreateInfo->arrayLayers;
image->info.levels = pCreateInfo->mipLevels;
- image->info.num_channels = 4; /* TODO: set this correctly */
+ image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
image->vk_format = pCreateInfo->format;
image->tiling = pCreateInfo->tiling;
0, RADEON_FLAG_VIRTUAL);
if (!image->bo) {
vk_free2(&device->alloc, alloc, image);
- return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
}
view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (view == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
radv_image_view_init(view, device, pCreateInfo);
view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!view)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
radv_buffer_view_init(view, device, pCreateInfo);
projects / mesa.git / blobdiff