if (device->physical_device->rad_info.chip_class < GFX8)
return false;
- if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
- (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
return false;
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
if (pCreateInfo->mipLevels > 1)
return false;
+ /* Do not enable TC-compatible HTILE if the image isn't readable by a
+ * shader because no texture fetches will happen.
+ */
+ if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+ VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
+ return false;
+
/* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
* tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
*/
return false;
if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
- const struct VkImageFormatListCreateInfoKHR *format_list =
- (const struct VkImageFormatListCreateInfoKHR *)
+ const struct VkImageFormatListCreateInfo *format_list =
+ (const struct VkImageFormatListCreateInfo *)
vk_find_struct_const(pCreateInfo->pNext,
- IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+ IMAGE_FORMAT_LIST_CREATE_INFO);
/* We have to ignore the existence of the list if viewFormatCount = 0 */
if (format_list && format_list->viewFormatCount) {
static bool
radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
{
- if (info->scanout)
- return true;
-
- if (!info->bo_metadata)
- return false;
-
- if (device->physical_device->rad_info.chip_class >= GFX9) {
- return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
- } else {
- return info->bo_metadata->u.legacy.scanout;
+ if (info->bo_metadata) {
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ return info->bo_metadata->u.gfx9.scanout;
+ else
+ return info->bo_metadata->u.legacy.scanout;
}
+
+ return info->scanout;
}
static bool
return false;
/* TODO: Enable DCC for storage images. */
- if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
- (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
return false;
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
&blendable);
if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
- const struct VkImageFormatListCreateInfoKHR *format_list =
- (const struct VkImageFormatListCreateInfoKHR *)
+ const struct VkImageFormatListCreateInfo *format_list =
+ (const struct VkImageFormatListCreateInfo *)
vk_find_struct_const(pCreateInfo->pNext,
- IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+ IMAGE_FORMAT_LIST_CREATE_INFO);
/* We have to ignore the existence of the list if viewFormatCount = 0 */
if (format_list && format_list->viewFormatCount) {
vk_format_is_compressed(image_format))
surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
- surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
-
if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
surface->flags |= RADEON_SURF_DISABLE_DCC;
S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
if (device->physical_device->rad_info.chip_class >= GFX10) {
- const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
+ const struct gfx10_format *fmt = gfx10_format_description(vk_format);
/* OOB_SELECT chooses the out-of-bounds check:
* - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
* else: swizzle_address >= NUM_RECORDS
*/
state[3] |= S_008F0C_FORMAT(fmt->img_format) |
- S_008F0C_OOB_SELECT(0) |
+ S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
S_008F0C_RESOURCE_LEVEL(1);
} else {
num_format = radv_translate_buffer_numformat(desc, first_non_void);
C_00A018_META_PIPE_ALIGNED;
if (meta_va) {
- struct gfx9_surf_meta_flags meta;
+ struct gfx9_surf_meta_flags meta = {
+ .rb_aligned = 1,
+ .pipe_aligned = 1,
+ };
if (image->dcc_offset)
meta = plane->surface.u.gfx9.dcc;
- else
- meta = plane->surface.u.gfx9.htile;
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
C_008F24_META_PIPE_ALIGNED &
C_008F24_META_RB_ALIGNED;
if (meta_va) {
- struct gfx9_surf_meta_flags meta;
+ struct gfx9_surf_meta_flags meta = {
+ .rb_aligned = 1,
+ .pipe_aligned = 1,
+ };
if (image->dcc_offset)
meta = plane->surface.u.gfx9.dcc;
- else
- meta = plane->surface.u.gfx9.htile;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
unsigned type;
desc = vk_format_description(vk_format);
- img_format = gfx10_format_table[vk_format].img_format;
+ img_format = gfx10_format_description(vk_format)->img_format;
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
fmask_state[4] = S_00A010_DEPTH(last_layer) |
S_00A010_BASE_ARRAY(first_layer);
fmask_state[5] = 0;
- fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
+ fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
fmask_state[7] = 0;
} else if (fmask_state)
memset(fmask_state, 0, 8 * 4);
fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
- fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
- S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
+ fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
+ S_008F24_META_RB_ALIGNED(1);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask_offset;
if (device->physical_device->rad_info.chip_class >= GFX9) {
metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+ metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
} else {
metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
struct radv_image *image,
uint64_t offset, uint32_t stride)
{
- struct radeon_surf *surface = &image->planes[0].surface;
- unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
-
- if (device->physical_device->rad_info.chip_class >= GFX9) {
- if (stride) {
- surface->u.gfx9.surf_pitch = stride;
- surface->u.gfx9.surf_slice_size =
- (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
- }
- surface->u.gfx9.surf_offset = offset;
- } else {
- surface->u.legacy.level[0].nblk_x = stride;
- surface->u.legacy.level[0].slice_size_dw =
- ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
-
- if (offset) {
- for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
- surface->u.legacy.level[i].offset += offset;
- }
-
- }
+ ac_surface_override_offset_stride(&device->physical_device->rad_info,
+ &image->planes[0].surface,
+ image->info.levels, offset, stride);
}
static void
static inline bool
radv_image_can_enable_fmask(struct radv_image *image)
{
- return image->info.samples > 1 && vk_format_is_color(image->vk_format);
+ return image->info.samples > 1 &&
+ image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
}
static inline bool
}
}
-bool radv_layout_has_htile(const struct radv_image *image,
- VkImageLayout layout,
- bool in_render_loop,
- unsigned queue_mask)
-{
- if (radv_image_is_tc_compat_htile(image))
- return layout != VK_IMAGE_LAYOUT_GENERAL;
-
- return radv_image_has_htile(image) &&
- (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
- (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
- queue_mask == (1u << RADV_QUEUE_GENERAL)));
-}
-
bool radv_layout_is_htile_compressed(const struct radv_image *image,
VkImageLayout layout,
bool in_render_loop,
unsigned queue_mask)
{
- if (radv_image_is_tc_compat_htile(image))
+ if (radv_image_is_tc_compat_htile(image)) {
+ if (layout == VK_IMAGE_LAYOUT_GENERAL &&
+ !in_render_loop &&
+ !(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
+ /* It should be safe to enable TC-compat HTILE with
+ * VK_IMAGE_LAYOUT_GENERAL if we are not in a render
+ * loop and if the image doesn't have the storage bit
+ * set. This improves performance for apps that use
+ * GENERAL for the main depth pass because this allows
+ * compression and this reduces the number of
+ * decompressions from/to GENERAL.
+ */
+ return true;
+ }
+
return layout != VK_IMAGE_LAYOUT_GENERAL;
+ }
return radv_image_has_htile(image) &&
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
+ layout == VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR ||
+ layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR ||
(layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
queue_mask == (1u << RADV_QUEUE_GENERAL)));
}
struct radeon_surf *surface = &plane->surface;
if (device->physical_device->rad_info.chip_class >= GFX9) {
- pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
+ uint64_t level_offset = surface->is_linear ? surface->u.gfx9.offset[level] : 0;
+
+ pLayout->offset = plane->offset + level_offset + surface->u.gfx9.surf_slice_size * layer;
if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
image->vk_format == VK_FORMAT_R32G32B32_SINT ||
image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
*/
pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
} else {
+ uint32_t pitch = surface->is_linear ? surface->u.gfx9.pitch[level] : surface->u.gfx9.surf_pitch;
+
assert(util_is_power_of_two_nonzero(surface->bpe));
- pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
+ pLayout->rowPitch = pitch * surface->bpe;
}
pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
projects / mesa.git / blobdiff