radv: Remove RANGE_SIZE usage

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 9633710bfdfd793cf3036b765c0142130650aa4a..44d049351406ee4a22d220685f092d702fff0e7e 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -437,8 +437,11 @@ radv_init_surface(struct radv_device *device,
                unreachable("unhandled image type");
        }
 
-       if (is_depth)
+       if (is_depth) {
                surface->flags |= RADEON_SURF_ZBUFFER;
+               if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
+                       surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
+       }
 
        if (is_stencil)
                surface->flags |= RADEON_SURF_SBUFFER;
@@ -449,8 +452,6 @@ radv_init_surface(struct radv_device *device,
            vk_format_is_compressed(image_format))
                surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
 
-       surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
-
        if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
                surface->flags |= RADEON_SURF_DISABLE_DCC;
 
@@ -518,7 +519,7 @@ radv_make_buffer_descriptor(struct radv_device *device,
                   S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
 
        if (device->physical_device->rad_info.chip_class >= GFX10) {
-               const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
+               const struct gfx10_format *fmt = gfx10_format_description(vk_format);
 
                /* OOB_SELECT chooses the out-of-bounds check:
                 *  - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
@@ -746,7 +747,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
        unsigned type;
 
        desc = vk_format_description(vk_format);
-       img_format = gfx10_format_table[vk_format].img_format;
+       img_format = gfx10_format_description(vk_format)->img_format;
 
        if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
                const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
@@ -1350,8 +1351,6 @@ static void radv_image_disable_htile(struct radv_image *image)
 {
        for (unsigned i = 0; i < image->plane_count; ++i)
                image->planes[i].surface.htile_size = 0;
-
-       image->tc_compatible_htile = false;
 }
 
 VkResult
@@ -1423,8 +1422,7 @@ radv_image_create_layout(struct radv_device *device,
                        /* Otherwise, try to enable HTILE for depth surfaces. */
                        if (radv_image_can_enable_htile(image) &&
                            !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
-                               if (!image->planes[0].surface.tc_compatible_htile_allowed)
-                                       image->tc_compatible_htile = false;
+                               image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
                                radv_image_alloc_htile(device, image);
                        } else {
                                radv_image_disable_htile(image);
@@ -1502,10 +1500,6 @@ radv_image_create(VkDevice _device,
                image->info.surf_index = &device->image_mrt_offset_counter;
        }
 
-       image->tc_compatible_htile =
-               radv_use_tc_compat_htile_for_image(device, create_info->vk_info,
-                                                  image->vk_format);
-
        for (unsigned plane = 0; plane < image->plane_count; ++plane) {
                radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format);
        }