radv: don't degrade tiling mode for small compressed or depth texture.

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 314964d64e5df88fcf4cb2a2cf61070f8e80441b..684e804cc9924f5dc64a0c9b94dfdab7a2d8f3c9 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -44,12 +44,16 @@ radv_choose_tiling(struct radv_device *Device,
                return RADEON_SURF_MODE_LINEAR_ALIGNED;
        }
 
-       /* Textures with a very small height are recommended to be linear. */
-       if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
-           /* Only very thin and long 2D textures should benefit from
-            * linear_aligned. */
-           (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
-               return RADEON_SURF_MODE_LINEAR_ALIGNED;
+       if (!vk_format_is_compressed(pCreateInfo->format) &&
+           !vk_format_is_depth_or_stencil(pCreateInfo->format)) {
+               /* Textures with a very small height are recommended to be linear. */
+               if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
+                   /* Only very thin and long 2D textures should benefit from
+                    * linear_aligned. */
+                   (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
+                       return RADEON_SURF_MODE_LINEAR_ALIGNED;
+
+       }
 
        /* MSAA resources must be 2D tiled. */
        if (pCreateInfo->samples > 1)
@@ -414,7 +418,7 @@ si_make_texture_descriptor(struct radv_device *device,
                state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
                state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
                                             util_logbase2(image->info.samples) :
-                                            last_level);
+                                            image->info.levels - 1);
        } else {
                state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
                state[4] |= S_008F20_DEPTH(depth - 1);
@@ -862,11 +866,10 @@ radv_image_create(VkDevice _device,
 static void
 radv_image_view_make_descriptor(struct radv_image_view *iview,
                                struct radv_device *device,
-                               const VkImageViewCreateInfo* pCreateInfo,
+                               const VkComponentMapping *components,
                                bool is_storage_image)
 {
-       RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
-       const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
+       struct radv_image *image = iview->image;
        bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
        uint32_t blk_w;
        uint32_t *descriptor;
@@ -886,20 +889,27 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
        si_make_texture_descriptor(device, image, is_storage_image,
                                   iview->type,
                                   iview->vk_format,
-                                  &pCreateInfo->components,
-                                  0, radv_get_levelCount(image, range) - 1,
-                                  range->baseArrayLayer,
-                                  range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
+                                  components,
+                                  0, iview->level_count - 1,
+                                  iview->base_layer,
+                                  iview->base_layer + iview->layer_count - 1,
                                   iview->extent.width,
                                   iview->extent.height,
                                   iview->extent.depth,
                                   descriptor,
                                   fmask_descriptor);
+
+       const struct legacy_surf_level *base_level_info = NULL;
+       if (device->physical_device->rad_info.chip_class <= GFX9) {
+               if (is_stencil)
+                       base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
+               else
+                       base_level_info = &image->surface.u.legacy.level[iview->base_mip];
+       }
        si_set_mutable_tex_desc_fields(device, image,
-                                      is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
-                                                 : &image->surface.u.legacy.level[range->baseMipLevel],
-                                      range->baseMipLevel,
-                                      range->baseMipLevel,
+                                      base_level_info,
+                                      iview->base_mip,
+                                      iview->base_mip,
                                       blk_w, is_stencil, descriptor);
 }
 
@@ -935,23 +945,34 @@ radv_image_view_init(struct radv_image_view *iview,
                iview->vk_format = vk_format_depth_only(iview->vk_format);
        }
 
-       iview->extent = (VkExtent3D) {
-               .width  = radv_minify(image->info.width , range->baseMipLevel),
-               .height = radv_minify(image->info.height, range->baseMipLevel),
-               .depth  = radv_minify(image->info.depth , range->baseMipLevel),
-       };
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
+               iview->extent = (VkExtent3D) {
+                       .width = image->info.width,
+                       .height = image->info.height,
+                       .depth = image->info.depth,
+               };
+       } else {
+               iview->extent = (VkExtent3D) {
+                       .width  = radv_minify(image->info.width , range->baseMipLevel),
+                       .height = radv_minify(image->info.height, range->baseMipLevel),
+                       .depth  = radv_minify(image->info.depth , range->baseMipLevel),
+               };
+       }
 
-       iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
-                                          vk_format_get_blockwidth(image->vk_format));
-       iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
-                                           vk_format_get_blockheight(image->vk_format));
+       if (iview->vk_format != image->vk_format) {
+               iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
+                                                  vk_format_get_blockwidth(image->vk_format));
+               iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
+                                                   vk_format_get_blockheight(image->vk_format));
+       }
 
        iview->base_layer = range->baseArrayLayer;
        iview->layer_count = radv_get_layerCount(image, range);
        iview->base_mip = range->baseMipLevel;
+       iview->level_count = radv_get_levelCount(image, range);
 
-       radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
-       radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
+       radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
+       radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
 }
 
 bool radv_layout_has_htile(const struct radv_image *image,