radv/gfx9: remove some leftover gfx6 descriptor setup.

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 8456d3ab1f6c2c92bf56732b1b540507b3755f43..8d3ff1a515ea416ac7d8308ee22c02dbb0d1e932 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -204,7 +204,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 {
        uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
        uint64_t va = gpu_address;
-       unsigned pitch = base_level_info->nblk_x * block_width;
        enum chip_class chip_class = device->physical_device->rad_info.chip_class;
        uint64_t meta_va = 0;
        if (chip_class >= GFX9) {
@@ -217,12 +216,10 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 
        state[0] = va >> 8;
        if (chip_class < GFX9)
-               state[0] |= image->surface.tile_swizzle;
+               if (base_level_info->mode == RADEON_SURF_MODE_2D)
+                       state[0] |= image->surface.tile_swizzle;
        state[1] &= C_008F14_BASE_ADDRESS_HI;
        state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
-       state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
-                                                            is_stencil));
-       state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
 
        if (chip_class >= VI) {
                state[6] &= C_008F28_COMPRESSION_EN;
@@ -483,7 +480,7 @@ si_make_texture_descriptor(struct radv_device *device,
 
                fmask_state[0] = va >> 8;
                if (device->physical_device->rad_info.chip_class < GFX9)
-                       fmask_state[0] |= image->surface.tile_swizzle;
+                       fmask_state[0] |= image->fmask.tile_swizzle;
                fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
                        S_008F14_DATA_FORMAT_GFX6(fmask_format) |
                        S_008F14_NUM_FORMAT_GFX6(num_format);
@@ -615,6 +612,9 @@ radv_image_get_fmask_info(struct radv_device *device,
        info.samples = 1;
        fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
 
+       if (!image->shareable)
+               info.surf_index = &device->fmask_mrt_offset_counter;
+
        /* Force 2D tiling if it wasn't set. This may occur when creating
         * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
         * destination buffer must have an FMASK too. */
@@ -643,8 +643,11 @@ radv_image_get_fmask_info(struct radv_device *device,
        out->tile_mode_index = fmask.u.legacy.tiling_index[0];
        out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
        out->bank_height = fmask.u.legacy.bankh;
+       out->tile_swizzle = fmask.tile_swizzle;
        out->alignment = MAX2(256, fmask.surf_alignment);
        out->size = fmask.surf_size;
+
+       assert(!out->tile_swizzle || !image->shareable);
 }
 
 static void