radv: gather info about PS inputs in the shader info pass

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 27843853af0f9cc8d0db35662d1e911a923c1d44..935224c5b6d71f69d7c7141db3bccb7f6d3d5cb7 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -142,13 +142,6 @@ radv_surface_has_scanout(struct radv_device *device, const struct radv_image_cre
        }
 }
 
-static bool
-radv_support_storage_dcc(const struct radv_physical_device *pdevice)
-{
-       return pdevice->rad_info.chip_class >= GFX10 &&
-              (pdevice->instance->perftest_flags & RADV_PERFTEST_STORAGE_DCC);
-}
-
 static bool
 radv_use_dcc_for_image(struct radv_device *device,
                       const struct radv_image *image,
@@ -168,8 +161,8 @@ radv_use_dcc_for_image(struct radv_device *device,
        if (image->shareable)
                return false;
 
-       if (((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)  &&
-            !radv_support_storage_dcc(device->physical_device))||
+       /* TODO: Enable DCC for storage images. */
+       if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
            (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
                return false;
 
@@ -1164,15 +1157,15 @@ radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
 
        /* + 8 for storing the clear values */
        image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
-       image->size = image->clear_value_offset + 8;
+       image->size = image->clear_value_offset + image->info.levels * 8;
        if (radv_image_is_tc_compat_htile(image) &&
-           device->physical_device->has_tc_compat_zrange_bug) {
+           device->physical_device->rad_info.has_tc_compat_zrange_bug) {
                /* Metadata for the TC-compatible HTILE hardware bug which
                 * have to be fixed by updating ZRANGE_PRECISION when doing
                 * fast depth clears to 0.0f.
                 */
                image->tc_compat_zrange_offset = image->size;
-               image->size = image->tc_compat_zrange_offset + 4;
+               image->size = image->tc_compat_zrange_offset + image->info.levels * 4;
        }
        image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
 }
@@ -1451,17 +1444,13 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
                else
                        base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
        }
-
-       if (is_storage_image && radv_image_has_dcc(iview->image) &&
-           !radv_support_storage_dcc(device->physical_device))
-               disable_compression = true;
        si_set_mutable_tex_desc_fields(device, image,
                                       base_level_info,
                                       plane_id,
                                       iview->base_mip,
                                       iview->base_mip,
                                       blk_w, is_stencil, is_storage_image,
-                                      disable_compression,
+                                      is_storage_image || disable_compression,
                                       descriptor->plane_descriptors[descriptor_plane_id]);
 }
 
@@ -1661,8 +1650,7 @@ bool radv_layout_dcc_compressed(const struct radv_device *device,
 {
        /* Don't compress compute transfer dst, as image stores are not supported. */
        if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
-           (queue_mask & (1u << RADV_QUEUE_COMPUTE)) &&
-           !radv_support_storage_dcc(device->physical_device))
+           (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
                return false;
 
        return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;