radv: gather info about PS inputs in the shader info pass

[mesa.git] / src / amd / vulkan / radv_image.c

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ed520833981799f5280ae88880d6d2fa7ccdcbfb..935224c5b6d71f69d7c7141db3bccb7f6d3d5cb7 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1157,15 +1157,15 @@ radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
 
        /* + 8 for storing the clear values */
        image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
-       image->size = image->clear_value_offset + 8;
+       image->size = image->clear_value_offset + image->info.levels * 8;
        if (radv_image_is_tc_compat_htile(image) &&
-           device->physical_device->has_tc_compat_zrange_bug) {
+           device->physical_device->rad_info.has_tc_compat_zrange_bug) {
                /* Metadata for the TC-compatible HTILE hardware bug which
                 * have to be fixed by updating ZRANGE_PRECISION when doing
                 * fast depth clears to 0.0f.
                 */
                image->tc_compat_zrange_offset = image->size;
-               image->size = image->tc_compat_zrange_offset + 4;
+               image->size = image->tc_compat_zrange_offset + image->info.levels * 4;
        }
        image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
 }
@@ -1612,7 +1612,7 @@ bool radv_layout_has_htile(const struct radv_image *image,
                            unsigned queue_mask)
 {
        if (radv_image_is_tc_compat_htile(image))
-               return !in_render_loop;
+               return layout != VK_IMAGE_LAYOUT_GENERAL;
 
        return radv_image_has_htile(image) &&
               (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
@@ -1626,7 +1626,7 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image,
                                      unsigned queue_mask)
 {
        if (radv_image_is_tc_compat_htile(image))
-               return !in_render_loop;
+               return layout != VK_IMAGE_LAYOUT_GENERAL;
 
        return radv_image_has_htile(image) &&
               (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
@@ -1642,7 +1642,8 @@ bool radv_layout_can_fast_clear(const struct radv_image *image,
        return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
 }
 
-bool radv_layout_dcc_compressed(const struct radv_image *image,
+bool radv_layout_dcc_compressed(const struct radv_device *device,
+                               const struct radv_image *image,
                                VkImageLayout layout,
                                bool in_render_loop,
                                unsigned queue_mask)
@@ -1652,7 +1653,7 @@ bool radv_layout_dcc_compressed(const struct radv_image *image,
            (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
                return false;
 
-       return radv_image_has_dcc(image) &&!in_render_loop;
+       return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
 }