#include "vk_util.h"
#include "radv_radeon_winsys.h"
#include "sid.h"
-#include "gfx9d.h"
#include "util/debug.h"
#include "util/u_atomic.h"
+
static unsigned
radv_choose_tiling(struct radv_device *device,
const struct radv_image_create_info *create_info)
(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
return false;
- /* TODO: Implement layout transitions with variable sample locations
- * before enabling HTILE for depth/stencil images created with this
- * flags because the depth decompress pass needs to know them.
- */
- if (pCreateInfo->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT)
- return false;
-
if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
return false;
* one format with everything else.
*/
for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
+ if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
+ continue;
+
if (pCreateInfo->format != format_list->pViewFormats[i])
return false;
}
return true;
}
+static bool
+radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
+{
+ if (info->scanout)
+ return true;
+
+ if (!info->bo_metadata)
+ return false;
+
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
+ } else {
+ return info->bo_metadata->u.legacy.scanout;
+ }
+}
+
static bool
radv_use_dcc_for_image(struct radv_device *device,
const struct radv_image *image,
if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
return false;
- /* FIXME: DCC is broken for shareable images starting with GFX9 */
- if (device->physical_device->rad_info.chip_class >= GFX9 &&
- image->shareable)
+ if (image->shareable)
return false;
/* TODO: Enable DCC for storage images. */
if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
return false;
- if (create_info->scanout)
+ if (radv_surface_has_scanout(device, create_info))
return false;
/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
/* compatibility is transitive, so we only need to check
* one format with everything else. */
for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
+ if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
+ continue;
+
if (!radv_dcc_formats_compatible(pCreateInfo->format,
format_list->pViewFormats[i]))
dcc_compatible_formats = false;
return true;
}
+static void
+radv_prefill_surface_from_metadata(struct radv_device *device,
+ struct radeon_surf *surface,
+ const struct radv_image_create_info *create_info)
+{
+ const struct radeon_bo_metadata *md = create_info->bo_metadata;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ if (md->u.gfx9.swizzle_mode > 0)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ else
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+
+ surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
+ } else {
+ surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
+ surface->u.legacy.bankw = md->u.legacy.bankw;
+ surface->u.legacy.bankh = md->u.legacy.bankh;
+ surface->u.legacy.tile_split = md->u.legacy.tile_split;
+ surface->u.legacy.mtilea = md->u.legacy.mtilea;
+ surface->u.legacy.num_banks = md->u.legacy.num_banks;
+
+ if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ else
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+
+ }
+}
+
static int
radv_init_surface(struct radv_device *device,
const struct radv_image *image,
if (surface->bpe == 3) {
surface->bpe = 4;
}
- surface->flags = RADEON_SURF_SET(array_mode, MODE);
+ if (create_info->bo_metadata) {
+ radv_prefill_surface_from_metadata(device, surface, create_info);
+ } else {
+ surface->flags = RADEON_SURF_SET(array_mode, MODE);
+ }
switch (pCreateInfo->imageType){
case VK_IMAGE_TYPE_1D:
if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
surface->flags |= RADEON_SURF_DISABLE_DCC;
- if (create_info->scanout)
+ if (radv_surface_has_scanout(device, create_info))
surface->flags |= RADEON_SURF_SCANOUT;
+
return 0;
}
num_format = radv_translate_buffer_numformat(desc, first_non_void);
data_format = radv_translate_buffer_dataformat(desc, first_non_void);
+ assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
+ assert(num_format != ~0);
+
va += offset;
state[0] = va;
state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
if (chip_class >= GFX9) {
state[3] &= C_008F1C_SW_MODE;
- state[4] &= C_008F20_PITCH_GFX9;
+ state[4] &= C_008F20_PITCH;
if (is_stencil) {
state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
- state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.stencil.epitch);
+ state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
} else {
state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
- state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.surf.epitch);
+ state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
}
state[5] &= C_008F24_META_DATA_ADDRESS &
state[3] &= C_008F1C_TILING_INDEX;
state[3] |= S_008F1C_TILING_INDEX(index);
- state[4] &= C_008F20_PITCH_GFX6;
- state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
+ state[4] &= C_008F20_PITCH;
+ state[4] |= S_008F20_PITCH(pitch - 1);
}
}
if (device->physical_device->rad_info.chip_class >= GFX9) {
fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
- S_008F20_PITCH_GFX9(image->planes[0].surface.u.gfx9.fmask.epitch);
+ S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
} else {
fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
- S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
+ S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
} else if (fmask_state)
struct radv_image *image,
struct radv_cmask_info *out)
{
- unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
- unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
- unsigned cl_width, cl_height;
-
assert(image->plane_count == 1);
if (device->physical_device->rad_info.chip_class >= GFX9) {
return;
}
- switch (num_pipes) {
- case 2:
- cl_width = 32;
- cl_height = 16;
- break;
- case 4:
- cl_width = 32;
- cl_height = 32;
- break;
- case 8:
- cl_width = 64;
- cl_height = 32;
- break;
- case 16: /* Hawaii */
- cl_width = 64;
- cl_height = 64;
- break;
- default:
- assert(0);
- return;
- }
-
- unsigned base_align = num_pipes * pipe_interleave_bytes;
-
- unsigned width = align(image->planes[0].surface.u.legacy.level[0].nblk_x, cl_width*8);
- unsigned height = align(image->planes[0].surface.u.legacy.level[0].nblk_y, cl_height*8);
- unsigned slice_elements = (width * height) / (8*8);
-
- /* Each element of CMASK is a nibble. */
- unsigned slice_bytes = slice_elements / 2;
-
- out->slice_tile_max = (width * height) / (128*128);
- if (out->slice_tile_max)
- out->slice_tile_max -= 1;
-
- out->alignment = MAX2(256, base_align);
- out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
- align(slice_bytes, base_align);
+ out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
+ out->alignment = image->planes[0].surface.cmask_alignment;
+ out->size = image->planes[0].surface.cmask_size;
}
static void
assert(image->plane_count == 1);
image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
- /* + 16 for storing the clear values + dcc pred */
+ /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
- image->fce_pred_offset = image->clear_value_offset + 8;
- image->dcc_pred_offset = image->clear_value_offset + 16;
- image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
+ image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
+ image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
+ image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
}
image->shareable = vk_find_struct_const(pCreateInfo->pNext,
EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
- if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
+ if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
+ !radv_surface_has_scanout(device, create_info) && !image->shareable) {
image->info.surf_index = &device->image_mrt_offset_counter;
}
projects / mesa.git / blobdiff