#include "sid.h"
#include "util/debug.h"
#include "util/u_atomic.h"
+#include "vulkan/util/vk_format.h"
+
+#include "gfx10_format_table.h"
static unsigned
radv_choose_tiling(struct radv_device *device,
if (pCreateInfo->mipLevels > 1)
return false;
+ /* Do not enable TC-compatible HTILE if the image isn't readable by a
+ * shader because no texture fetches will happen.
+ */
+ if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+ VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
+ return false;
+
/* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
* tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
*/
return true;
}
+static inline bool
+radv_use_fmask_for_image(const struct radv_image *image)
+{
+ return image->info.samples > 1 &&
+ image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
+}
+
static bool
radv_use_tc_compat_cmask_for_image(struct radv_device *device,
struct radv_image *image)
unreachable("unhandled image type");
}
+ /* Required for clearing/initializing a specific layer on GFX8. */
+ surface->flags |= RADEON_SURF_CONTIGUOUS_DCC_LAYERS;
+
if (is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
vk_format_is_compressed(image_format))
surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
- surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
-
if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
surface->flags |= RADEON_SURF_DISABLE_DCC;
+ if (!radv_use_fmask_for_image(image))
+ surface->flags |= RADEON_SURF_NO_FMASK;
+
return 0;
}
S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
if (device->physical_device->rad_info.chip_class >= GFX10) {
- const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
+ const struct gfx10_format *fmt = &gfx10_format_table[vk_format_to_pipe_format(vk_format)];
/* OOB_SELECT chooses the out-of-bounds check:
* - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
C_00A018_META_PIPE_ALIGNED;
if (meta_va) {
- struct gfx9_surf_meta_flags meta;
+ struct gfx9_surf_meta_flags meta = {
+ .rb_aligned = 1,
+ .pipe_aligned = 1,
+ };
if (image->dcc_offset)
meta = plane->surface.u.gfx9.dcc;
- else
- meta = plane->surface.u.gfx9.htile;
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
C_008F24_META_PIPE_ALIGNED &
C_008F24_META_RB_ALIGNED;
if (meta_va) {
- struct gfx9_surf_meta_flags meta;
+ struct gfx9_surf_meta_flags meta = {
+ .rb_aligned = 1,
+ .pipe_aligned = 1,
+ };
if (image->dcc_offset)
meta = plane->surface.u.gfx9.dcc;
- else
- meta = plane->surface.u.gfx9.htile;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
unsigned type;
desc = vk_format_description(vk_format);
- img_format = gfx10_format_table[vk_format].img_format;
+ img_format = gfx10_format_table[vk_format_to_pipe_format(vk_format)].img_format;
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
fmask_state[4] = S_00A010_DEPTH(last_layer) |
S_00A010_BASE_ARRAY(first_layer);
fmask_state[5] = 0;
- fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
+ fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
fmask_state[7] = 0;
} else if (fmask_state)
memset(fmask_state, 0, 8 * 4);
fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
- fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
- S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
+ fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
+ S_008F24_META_RB_ALIGNED(1);
if (radv_image_is_tc_compat_cmask(image)) {
va = gpu_address + image->offset + image->cmask_offset;
struct radv_image *image,
uint64_t offset, uint32_t stride)
{
- struct radeon_surf *surface = &image->planes[0].surface;
- unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
-
- if (device->physical_device->rad_info.chip_class >= GFX9) {
- if (stride) {
- surface->u.gfx9.surf_pitch = stride;
- surface->u.gfx9.surf_slice_size =
- (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
- }
- surface->u.gfx9.surf_offset = offset;
- } else {
- surface->u.legacy.level[0].nblk_x = stride;
- surface->u.legacy.level[0].slice_size_dw =
- ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
-
- if (offset) {
- for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
- surface->u.legacy.level[i].offset += offset;
- }
-
- }
+ ac_surface_override_offset_stride(&device->physical_device->rad_info,
+ &image->planes[0].surface,
+ image->info.levels, offset, stride);
}
static void
!radv_image_has_dcc(image))
return false;
- /* On GFX8, DCC layers can be interleaved and it's currently only
- * enabled if slice size is equal to the per slice fast clear size
- * because the driver assumes that portions of multiple layers are
- * contiguous during fast clears.
- */
- if (image->info.array_size > 1) {
- const struct legacy_surf_level *surf_level =
- &image->planes[0].surface.u.legacy.level[0];
-
- assert(device->physical_device->rad_info.chip_class == GFX8);
-
- if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
- return false;
- }
-
return true;
}
return radv_image_can_enable_dcc_or_cmask(image) &&
image->info.levels == 1 &&
- image->info.depth == 1 &&
- !image->planes[0].surface.is_linear;
-}
-
-static inline bool
-radv_image_can_enable_fmask(struct radv_image *image)
-{
- return image->info.samples > 1 && vk_format_is_color(image->vk_format);
+ image->info.depth == 1;
}
static inline bool
info.height /= desc->height_divisor;
}
+ if (create_info.no_metadata_planes || image->plane_count > 1) {
+ image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC |
+ RADEON_SURF_NO_FMASK |
+ RADEON_SURF_NO_HTILE;
+ }
+
device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
}
- if (!create_info.no_metadata_planes) {
- /* Try to enable DCC first. */
- if (radv_image_can_enable_dcc(device, image)) {
- radv_image_alloc_dcc(image);
- if (image->info.samples > 1) {
- /* CMASK should be enabled because DCC fast
- * clear with MSAA needs it.
- */
- assert(radv_image_can_enable_cmask(image));
- radv_image_alloc_cmask(device, image);
- }
- } else {
- /* When DCC cannot be enabled, try CMASK. */
- radv_image_disable_dcc(image);
- if (radv_image_can_enable_cmask(image)) {
- radv_image_alloc_cmask(device, image);
- }
+ /* Try to enable DCC first. */
+ if (radv_image_can_enable_dcc(device, image)) {
+ radv_image_alloc_dcc(image);
+ if (image->info.samples > 1) {
+ /* CMASK should be enabled because DCC fast
+ * clear with MSAA needs it.
+ */
+ assert(radv_image_can_enable_cmask(image));
+ radv_image_alloc_cmask(device, image);
+ }
+ } else {
+ /* When DCC cannot be enabled, try CMASK. */
+ radv_image_disable_dcc(image);
+ if (radv_image_can_enable_cmask(image)) {
+ radv_image_alloc_cmask(device, image);
}
+ }
- /* Try to enable FMASK for multisampled images. */
- if (radv_image_can_enable_fmask(image)) {
- radv_image_alloc_fmask(device, image);
+ /* Try to enable FMASK for multisampled images. */
+ if (image->planes[0].surface.fmask_size) {
+ radv_image_alloc_fmask(device, image);
- if (radv_use_tc_compat_cmask_for_image(device, image))
- image->tc_compatible_cmask = true;
+ if (radv_use_tc_compat_cmask_for_image(device, image))
+ image->tc_compatible_cmask = true;
+ } else {
+ /* Otherwise, try to enable HTILE for depth surfaces. */
+ if (radv_image_can_enable_htile(image) &&
+ !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
+ image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+ radv_image_alloc_htile(device, image);
} else {
- /* Otherwise, try to enable HTILE for depth surfaces. */
- if (radv_image_can_enable_htile(image) &&
- !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
- image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
- radv_image_alloc_htile(device, image);
- } else {
- radv_image_disable_htile(image);
- }
+ radv_image_disable_htile(image);
}
- } else {
- radv_image_disable_dcc(image);
- radv_image_disable_htile(image);
}
assert(image->planes[0].surface.surf_size);
radv_assert(pCreateInfo->extent.height > 0);
radv_assert(pCreateInfo->extent.depth > 0);
- image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
+ image = vk_zalloc2(&device->vk.alloc, alloc, image_struct_size, 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!image)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &image->base, VK_OBJECT_TYPE_IMAGE);
+
image->type = pCreateInfo->imageType;
image->info.width = pCreateInfo->extent.width;
image->info.height = pCreateInfo->extent.height;
image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
if (!image->bo) {
- vk_free2(&device->alloc, alloc, image);
+ vk_free2(&device->vk.alloc, alloc, image);
return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
}
bool in_render_loop,
unsigned queue_mask)
{
- if (radv_image_is_tc_compat_htile(image))
+ if (radv_image_is_tc_compat_htile(image)) {
+ if (layout == VK_IMAGE_LAYOUT_GENERAL &&
+ !in_render_loop &&
+ !(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
+ /* It should be safe to enable TC-compat HTILE with
+ * VK_IMAGE_LAYOUT_GENERAL if we are not in a render
+ * loop and if the image doesn't have the storage bit
+ * set. This improves performance for apps that use
+ * GENERAL for the main depth pass because this allows
+ * compression and this reduces the number of
+ * decompressions from/to GENERAL.
+ */
+ return true;
+ }
+
return layout != VK_IMAGE_LAYOUT_GENERAL;
+ }
return radv_image_has_htile(image) &&
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
if (image->owned_memory != VK_NULL_HANDLE)
radv_FreeMemory(_device, image->owned_memory, pAllocator);
- vk_free2(&device->alloc, pAllocator, image);
+ vk_object_base_finish(&image->base);
+ vk_free2(&device->vk.alloc, pAllocator, image);
}
void radv_GetImageSubresourceLayout(
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_image_view *view;
- view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
+ view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (view == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &view->base,
+ VK_OBJECT_TYPE_IMAGE_VIEW);
+
radv_image_view_init(view, device, pCreateInfo, NULL);
*pView = radv_image_view_to_handle(view);
if (!iview)
return;
- vk_free2(&device->alloc, pAllocator, iview);
+
+ vk_object_base_finish(&iview->base);
+ vk_free2(&device->vk.alloc, pAllocator, iview);
}
void radv_buffer_view_init(struct radv_buffer_view *view,
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_buffer_view *view;
- view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
+ view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!view)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_object_base_init(&device->vk, &view->base,
+ VK_OBJECT_TYPE_BUFFER_VIEW);
+
radv_buffer_view_init(view, device, pCreateInfo);
*pView = radv_buffer_view_to_handle(view);
if (!view)
return;
- vk_free2(&device->alloc, pAllocator, view);
+ vk_object_base_finish(&view->base);
+ vk_free2(&device->vk.alloc, pAllocator, view);
}
projects / mesa.git / blobdiff